Devon C. Kramer

Array ( [id] => 3491546 [patent_doc_number] => 05475244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'MIS transistor having second conductivity type source and drain regions sandwiching a channel region of a first conductivity type of a first semiconductor material formed on an insulating substrate, and a gate electrode formed on a main surface' [patent_app_type] => 1 [patent_app_number] => 8/037681 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 93 [patent_no_of_words] => 12957 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475244.pdf [firstpage_image] =>[orig_patent_app_number] => 037681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3415995 [patent_doc_number] => 05412237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Semiconductor device with improved element isolation and operation rate' [patent_app_type] => 1 [patent_app_number] => 8/026359 [patent_app_country] => US [patent_app_date] => 1993-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 47 [patent_no_of_words] => 6125 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/412/05412237.pdf [firstpage_image] =>[orig_patent_app_number] => 026359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3702110 [patent_doc_number] => 05677552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Optical control circuit for an optical pnpn thyristor' [patent_app_type] => 1 [patent_app_number] => 8/023124 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2777 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677552.pdf [firstpage_image] =>[orig_patent_app_number] => 023124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3780316 [patent_doc_number] => 05808347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'MIS transistor with gate sidewall insulating layer' [patent_app_type] => 1 [patent_app_number] => 8/023122 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4511 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808347.pdf [firstpage_image] =>[orig_patent_app_number] => 023122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112391 [patent_doc_number] => 05408118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Vertical double diffused MOSFET having a low breakdown voltage and constituting a power semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/023192 [patent_app_country] => US [patent_app_date] => 1993-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 10522 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408118.pdf [firstpage_image] =>[orig_patent_app_number] => 023192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3079781 [patent_doc_number] => 05296728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Compound semiconductor device with different gate-source and gate-drain spacings' [patent_app_type] => 1 [patent_app_number] => 8/023151 [patent_app_country] => US [patent_app_date] => 1993-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2794 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296728.pdf [firstpage_image] =>[orig_patent_app_number] => 023151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3092600 [patent_doc_number] => 05278431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Diamond rectifying contact with undoped diamond layer' [patent_app_type] => 1 [patent_app_number] => 8/021204 [patent_app_country] => US [patent_app_date] => 1993-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3726 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278431.pdf [firstpage_image] =>[orig_patent_app_number] => 021204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061789 [patent_doc_number] => 05338961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'High power MOSFET with low on-resistance and high breakdown voltage' [patent_app_type] => 1 [patent_app_number] => 8/017511 [patent_app_country] => US [patent_app_date] => 1993-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3770 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338961.pdf [firstpage_image] =>[orig_patent_app_number] => 017511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3450089 [patent_doc_number] => 05420447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Double buffer base gate array cell' [patent_app_type] => 1 [patent_app_number] => 8/011390 [patent_app_country] => US [patent_app_date] => 1993-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6692 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420447.pdf [firstpage_image] =>[orig_patent_app_number] => 011390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3012278 [patent_doc_number] => 05355002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Structure of high yield thin film transistors' [patent_app_type] => 1 [patent_app_number] => 8/005794 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 27 [patent_no_of_words] => 3567 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355002.pdf [firstpage_image] =>[orig_patent_app_number] => 005794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3044433 [patent_doc_number] => 05334580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'Superconducting device having superconducting weak coupling' [patent_app_type] => 1 [patent_app_number] => 8/004247 [patent_app_country] => US [patent_app_date] => 1993-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5743 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/334/05334580.pdf [firstpage_image] =>[orig_patent_app_number] => 004247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463674 [patent_doc_number] => 05382825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Spiral edge passivation structure for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/001752 [patent_app_country] => US [patent_app_date] => 1993-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3420 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/382/05382825.pdf [firstpage_image] =>[orig_patent_app_number] => 001752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2908350 [patent_doc_number] => 05248893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone' [patent_app_type] => 1 [patent_app_number] => 8/000593 [patent_app_country] => US [patent_app_date] => 1993-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2433 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/248/05248893.pdf [firstpage_image] =>[orig_patent_app_number] => 000593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3514968 [patent_doc_number] => 05563439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Variable operation speed MOS transistor' [patent_app_type] => 1 [patent_app_number] => 7/995862 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3379 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563439.pdf [firstpage_image] =>[orig_patent_app_number] => 995862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4224805 [patent_doc_number] => 06040617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Structure to provide junction breakdown stability for deep trench devices' [patent_app_type] => 1 [patent_app_number] => 7/995582 [patent_app_country] => US [patent_app_date] => 1992-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1817 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040617.pdf [firstpage_image] =>[orig_patent_app_number] => 995582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3117812 [patent_doc_number] => 05396087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Insulated gate bipolar transistor with reduced susceptibility to parasitic latch-up' [patent_app_type] => 1 [patent_app_number] => 7/990062 [patent_app_country] => US [patent_app_date] => 1992-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3903 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396087.pdf [firstpage_image] =>[orig_patent_app_number] => 990062 [rel_patent_id] =>[rel_patent_doc_number] =>)