
Devon C. Kramer
Supervisory Patent Examiner (ID: 1983, Phone: (571)272-7118 , Office: P/3746 )
| Most Active Art Unit | 3683 |
| Art Unit(s) | 3683, 3741, 3613, 3746 |
| Total Applications | 1035 |
| Issued Applications | 672 |
| Pending Applications | 81 |
| Abandoned Applications | 283 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7030855
[patent_doc_number] => 20050029557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'High-breakdown-voltage semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/942011
[patent_app_country] => US
[patent_app_date] => 2004-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 14125
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20050029557.pdf
[firstpage_image] =>[orig_patent_app_number] => 10942011
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/942011 | High-breakdown-voltage semiconductor device | Sep 15, 2004 | Issued |
Array
(
[id] => 6963935
[patent_doc_number] => 20050230832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-20
[patent_title] => 'Three-level unitary interconnect structure'
[patent_app_type] => utility
[patent_app_number] => 10/925225
[patent_app_country] => US
[patent_app_date] => 2004-08-24
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10925225
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925225 | Three-level unitary interconnect structure | Aug 23, 2004 | Abandoned |
Array
(
[id] => 7086552
[patent_doc_number] => 20050006664
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Semisonductor device'
[patent_app_type] => utility
[patent_app_number] => 10/909425
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[patent_app_date] => 2004-08-03
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[firstpage_image] =>[orig_patent_app_number] => 10909425
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/909425 | Semisonductor device | Aug 2, 2004 | Abandoned |
Array
(
[id] => 7132791
[patent_doc_number] => 20050179027
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[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Nitride based semiconductor light-emitting device'
[patent_app_type] => utility
[patent_app_number] => 10/890215
[patent_app_country] => US
[patent_app_date] => 2004-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/890215 | Nitride based semiconductor light-emitting device | Jul 13, 2004 | Abandoned |
Array
(
[id] => 963622
[patent_doc_number] => 06949434
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[patent_kind] => B2
[patent_issue_date] => 2005-09-27
[patent_title] => 'Method of manufacturing a vertical semiconductor device'
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[pdf_file] => patents/06/949/06949434.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/880048 | Method of manufacturing a vertical semiconductor device | Jun 28, 2004 | Issued |
Array
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[patent_issue_date] => 2004-11-25
[patent_title] => 'Semiconductor device and manufacturing method thereof'
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Array
(
[id] => 703121
[patent_doc_number] => 07064410
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[patent_issue_date] => 2006-06-20
[patent_title] => 'MOS antifuse with low post-program resistance'
[patent_app_type] => utility
[patent_app_number] => 10/872173
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[patent_app_date] => 2004-06-18
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[pdf_file] => patents/07/064/07064410.pdf
[firstpage_image] =>[orig_patent_app_number] => 10872173
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/872173 | MOS antifuse with low post-program resistance | Jun 17, 2004 | Issued |
Array
(
[id] => 7363110
[patent_doc_number] => 20040217417
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[patent_issue_date] => 2004-11-04
[patent_title] => 'High voltage device and method for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/855523
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[patent_app_date] => 2004-05-28
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[pdf_file] => publications/A1/0217/20040217417.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/855523 | High voltage device and method for fabricating the same | May 27, 2004 | Abandoned |
Array
(
[id] => 7002333
[patent_doc_number] => 20050167646
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[patent_issue_date] => 2005-08-04
[patent_title] => 'Nanosubstrate with conductive zone and method for its selective preparation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/854746 | Nanosubstrate with conductive zone and method for its selective preparation | May 26, 2004 | Abandoned |
Array
(
[id] => 7411653
[patent_doc_number] => 20040207027
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[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Semiconductor switching device and method'
[patent_app_type] => new
[patent_app_number] => 10/840486
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[patent_app_date] => 2004-05-06
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[firstpage_image] =>[orig_patent_app_number] => 10840486
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/840486 | Semiconductor bidirectional switching device | May 5, 2004 | Issued |
Array
(
[id] => 7067034
[patent_doc_number] => 20050242416
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[patent_issue_date] => 2005-11-03
[patent_title] => 'LOW-CAPACITANCE BONDING PAD FOR SEMICONDUCTOR DEVICE'
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[patent_app_number] => 10/709366
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709366 | LOW-CAPACITANCE BONDING PAD FOR SEMICONDUCTOR DEVICE | Apr 28, 2004 | Abandoned |
Array
(
[id] => 690491
[patent_doc_number] => 07074686
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[patent_issue_date] => 2006-07-11
[patent_title] => 'Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications'
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[patent_app_number] => 10/824289
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/824289 | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications | Apr 13, 2004 | Issued |
Array
(
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[patent_title] => 'Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby'
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Array
(
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[patent_title] => 'Stacked semiconductor device'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804578 | Method of forming shallow doped junctions having a variable profile gradation of dopants | Mar 18, 2004 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/790983 | Non-uniform power semiconductor and method for making non-uniform power semiconductor | Feb 29, 2004 | Issued |