Dewanda A Samuel

Array ( [id] => 17985945 [patent_doc_number] => 20220351982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER [patent_app_type] => utility [patent_app_number] => 17/246209 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17319218 [patent_doc_number] => 20210408268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Method for Manufacturing Semiconductor Device [patent_app_type] => utility [patent_app_number] => 17/224406 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18343494 [patent_doc_number] => 11640978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Low-k feature formation processes and structures formed thereby [patent_app_type] => utility [patent_app_number] => 17/222303 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17536633 [patent_doc_number] => 20220115242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/218886 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17509108 [patent_doc_number] => 20220102211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/214417 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17145344 [patent_doc_number] => 20210313357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => PHOTODETECTOR, DISPLAY SUBSTRATE, AND METHOD OF MANUFACTURING PHOTODETECTOR [patent_app_type] => utility [patent_app_number] => 17/204057 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17870875 [patent_doc_number] => 20220293612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR DEVICE HAVING STI REGION [patent_app_type] => utility [patent_app_number] => 17/202146 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17870888 [patent_doc_number] => 20220293625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES WITH NITROGEN-RICH INSULATIVE STRUCTURES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/200169 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19108627 [patent_doc_number] => 11961741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Method for fabricating layer structure having target topological profile [patent_app_type] => utility [patent_app_number] => 17/192865 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 14694 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17085451 [patent_doc_number] => 20210280458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/249540 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17737960 [patent_doc_number] => 20220223422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => Surface Oxidation Control of Metal Gates Using Capping Layer [patent_app_type] => utility [patent_app_number] => 17/191105 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16902653 [patent_doc_number] => 20210181569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MANUFACTURING METHOD FOR LIQUID CRYSTAL DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/187945 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17795802 [patent_doc_number] => 20220254894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => ELECTRONIC DEVICE INCLUDING A GATE STRUCTURE AND A PROCESS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/172243 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17025648 [patent_doc_number] => 20210249520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MULTIPLE GATE SIDEWALL SPACER WIDTHS [patent_app_type] => utility [patent_app_number] => 17/168430 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16951814 [patent_doc_number] => 20210210506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => VERTICAL THIN-FILM TRANSISTOR AND APPLICATION AS BIT-LINE CONNECTOR FOR 3-DIMENSIONAL MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 17/161504 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19138154 [patent_doc_number] => 11973130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized MOSFET and SONOS co-integration [patent_app_type] => utility [patent_app_number] => 17/159319 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5121 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16827727 [patent_doc_number] => 20210143020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => DOUBLE PATTERNING METHOD [patent_app_type] => utility [patent_app_number] => 17/152839 [patent_app_country] => US [patent_app_date] => 2021-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16981406 [patent_doc_number] => 20210225643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => METHOD FOR DEPOSITION OF SILICON NITRIDE LAYER USING PRETREATMENT, STRUCTURE FORMED USING THE METHOD, AND SYSTEM FOR PERFORMING THE METHOD [patent_app_type] => utility [patent_app_number] => 17/152592 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17417280 [patent_doc_number] => 20220052184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => Profile Control In Forming Epitaxy Regions for Transistors [patent_app_type] => utility [patent_app_number] => 17/148220 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17723326 [patent_doc_number] => 20220216048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => DOPED SILICON NITRIDE FOR 3D NAND [patent_app_type] => utility [patent_app_number] => 17/142641 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142641 [rel_patent_id] =>[rel_patent_doc_number] =>)