Search

Dewanda A Samuel

Examiner (ID: 12569, Phone: (571)270-1213 , Office: P/2464 )

Most Active Art Unit
2464
Art Unit(s)
2616, 2464, 2416
Total Applications
590
Issued Applications
492
Pending Applications
2
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17477683 [patent_doc_number] => 20220085187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => VOID ELIMINATION FOR GAP-FILLING IN HIGH-ASPECT RATIO TRENCHES [patent_app_type] => utility [patent_app_number] => 17/140897 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140897 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140897
Void elimination for gap-filling in high-aspect ratio trenches Jan 3, 2021 Issued
Array ( [id] => 16715601 [patent_doc_number] => 20210082748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Method of Forming Trenches [patent_app_type] => utility [patent_app_number] => 17/107273 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107273
Method of Forming Trenches Nov 29, 2020 Pending
Array ( [id] => 17203736 [patent_doc_number] => 20210343831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/101209 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101209
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME Nov 22, 2020 Abandoned
Array ( [id] => 17630551 [patent_doc_number] => 20220165566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => CONFORMAL SILICON-GERMANIUM FILM DEPOSITION [patent_app_type] => utility [patent_app_number] => 16/953569 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953569 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953569
CONFORMAL SILICON-GERMANIUM FILM DEPOSITION Nov 19, 2020 Pending
Array ( [id] => 17373932 [patent_doc_number] => 20220028984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => INTERLAYER DIELECTRIC LAYER STRUCTURE FOR POWER MOS DEVICE AND METHOD FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/096109 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096109
INTERLAYER DIELECTRIC LAYER STRUCTURE FOR POWER MOS DEVICE AND METHOD FOR MAKING THE SAME Nov 11, 2020 Abandoned
Array ( [id] => 19123530 [patent_doc_number] => 11967524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => 3D NAND gate stack reinforcement [patent_app_type] => utility [patent_app_number] => 17/089221 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 11274 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089221
3D NAND gate stack reinforcement Nov 3, 2020 Issued
Array ( [id] => 17566820 [patent_doc_number] => 20220130969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => POWER DEVICE WITH A CONTACT HOLE ON A SLOPED ILD REGION [patent_app_type] => utility [patent_app_number] => 16/949272 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949272 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949272
POWER DEVICE WITH A CONTACT HOLE ON A SLOPED ILD REGION Oct 21, 2020 Abandoned
Array ( [id] => 16904797 [patent_doc_number] => 20210183713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => Gate Formation Of Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/075313 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075313
Gate formation of semiconductor devices Oct 19, 2020 Issued
Array ( [id] => 16631778 [patent_doc_number] => 20210050431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => Semiconductor Device Gate Spacer Structures and Methods Thereof [patent_app_type] => utility [patent_app_number] => 17/074265 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074265
Semiconductor device gate spacer structures and methods thereof Oct 18, 2020 Issued
Array ( [id] => 17247314 [patent_doc_number] => 20210367059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => Dummy Fin Profile Control to Enlarge Gate Process Window [patent_app_type] => utility [patent_app_number] => 17/069460 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069460
Dummy FIN profile control to enlarge gate process window Oct 12, 2020 Issued
Array ( [id] => 17978806 [patent_doc_number] => 11495681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/067775 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8683 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067775
Semiconductor device and manufacturing method thereof Oct 11, 2020 Issued
Array ( [id] => 18331758 [patent_doc_number] => 11637011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Method of topology-selective film formation of silicon oxide [patent_app_type] => utility [patent_app_number] => 17/068495 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10910 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068495
Method of topology-selective film formation of silicon oxide Oct 11, 2020 Issued
Array ( [id] => 16617475 [patent_doc_number] => 20210036128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => Structure and Formation Method of Semiconductor Device Structure with Gate Stack [patent_app_type] => utility [patent_app_number] => 17/066102 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066102
Structure and formation method of semiconductor device structure with gate stack Oct 7, 2020 Issued
Array ( [id] => 17523035 [patent_doc_number] => 20220108884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => SYSTEMS AND METHODS FOR FORMING UV-CURED LOW-K DIELECTRIC FILMS [patent_app_type] => utility [patent_app_number] => 17/063358 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063358
Systems and methods for forming UV-cured low-k dielectric films Oct 4, 2020 Issued
Array ( [id] => 17509048 [patent_doc_number] => 20220102151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Germanium Hump Reduction [patent_app_type] => utility [patent_app_number] => 17/038258 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038258
Germanium hump reduction Sep 29, 2020 Issued
Array ( [id] => 16598528 [patent_doc_number] => 20210025059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => PLASMA ATOMIC LAYER DEPOSITION [patent_app_type] => utility [patent_app_number] => 17/039632 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039632
PLASMA ATOMIC LAYER DEPOSITION Sep 29, 2020 Pending
Array ( [id] => 16752387 [patent_doc_number] => 20210104399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => METHODS FOR FORMING A TOPOGRAPHICALLY SELECTIVE SILICON OXIDE FILM BY A CYCLICAL PLASMA-ENHANCED DEPOSITION PROCESS [patent_app_type] => utility [patent_app_number] => 17/037481 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037481
Methods for forming a topographically selective silicon oxide film by a cyclical plasma-enhanced deposition process Sep 28, 2020 Issued
Array ( [id] => 16560454 [patent_doc_number] => 20210005603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/025497 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025497
Semiconductor device and method for fabricating the same Sep 17, 2020 Issued
Array ( [id] => 17477374 [patent_doc_number] => 20220084878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS [patent_app_type] => utility [patent_app_number] => 17/023391 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023391
Fabricating method of transistors without dishing occurred during CMP process Sep 16, 2020 Issued
Array ( [id] => 17941654 [patent_doc_number] => 11476113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium [patent_app_type] => utility [patent_app_number] => 17/021738 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10248 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021738
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium Sep 14, 2020 Issued
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