Search

Dhaval V. Patel

Examiner (ID: 4462, Phone: (571)270-1818 , Office: P/2631 )

Most Active Art Unit
2631
Art Unit(s)
2611, 2631
Total Applications
1587
Issued Applications
1334
Pending Applications
84
Abandoned Applications
204

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6839932 [patent_doc_number] => 20030037272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Bus system and method for achieving a stable bus redundancy' [patent_app_type] => new [patent_app_number] => 09/735515 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1857 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037272.pdf [firstpage_image] =>[orig_patent_app_number] => 09735515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735515
Bus system and method for achieving a stable bus redundancy Dec 13, 2000 Issued
Array ( [id] => 1240825 [patent_doc_number] => 06691194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Selective association of lock override procedures with queued multimodal lock' [patent_app_type] => B1 [patent_app_number] => 09/724044 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11357 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691194.pdf [firstpage_image] =>[orig_patent_app_number] => 09724044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724044
Selective association of lock override procedures with queued multimodal lock Nov 27, 2000 Issued
Array ( [id] => 1178913 [patent_doc_number] => 06757777 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Bus master switching unit' [patent_app_type] => B1 [patent_app_number] => 09/647704 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4069 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757777.pdf [firstpage_image] =>[orig_patent_app_number] => 09647704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/647704
Bus master switching unit Nov 21, 2000 Issued
Array ( [id] => 1020875 [patent_doc_number] => 06892262 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Serial bus interface device' [patent_app_type] => utility [patent_app_number] => 09/714304 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892262.pdf [firstpage_image] =>[orig_patent_app_number] => 09714304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714304
Serial bus interface device Nov 16, 2000 Issued
Array ( [id] => 1229030 [patent_doc_number] => 06701401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method for testing a USB port and the device for the same' [patent_app_type] => B1 [patent_app_number] => 09/706840 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1633 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701401.pdf [firstpage_image] =>[orig_patent_app_number] => 09706840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706840
Method for testing a USB port and the device for the same Nov 6, 2000 Issued
Array ( [id] => 1243087 [patent_doc_number] => 06684286 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'High-speed block transfer circuit' [patent_app_type] => B1 [patent_app_number] => 09/704719 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6558 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684286.pdf [firstpage_image] =>[orig_patent_app_number] => 09704719 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/704719
High-speed block transfer circuit Nov 2, 2000 Issued
Array ( [id] => 1240823 [patent_doc_number] => 06691193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses' [patent_app_type] => B1 [patent_app_number] => 09/691391 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3456 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691193.pdf [firstpage_image] =>[orig_patent_app_number] => 09691391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/691391
Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses Oct 17, 2000 Issued
Array ( [id] => 7630014 [patent_doc_number] => 06636925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Bus interface circuit preparation apparatus and recording medium' [patent_app_type] => B1 [patent_app_number] => 09/686928 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 11366 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636925.pdf [firstpage_image] =>[orig_patent_app_number] => 09686928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/686928
Bus interface circuit preparation apparatus and recording medium Oct 10, 2000 Issued
Array ( [id] => 7633107 [patent_doc_number] => 06658513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Managing locks affected by planned or unplanned reconfiguration of locking facilities' [patent_app_type] => B1 [patent_app_number] => 09/685623 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 14 [patent_no_of_words] => 7107 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658513.pdf [firstpage_image] =>[orig_patent_app_number] => 09685623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685623
Managing locks affected by planned or unplanned reconfiguration of locking facilities Oct 9, 2000 Issued
Array ( [id] => 1288904 [patent_doc_number] => 06647450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Multiprocessor computer systems with command FIFO buffer at each target device' [patent_app_type] => B1 [patent_app_number] => 09/680652 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2547 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647450.pdf [firstpage_image] =>[orig_patent_app_number] => 09680652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680652
Multiprocessor computer systems with command FIFO buffer at each target device Oct 5, 2000 Issued
Array ( [id] => 1296985 [patent_doc_number] => 06633938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Independent reset of arbiters and agents to allow for delayed agent reset' [patent_app_type] => B1 [patent_app_number] => 09/680525 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6909 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633938.pdf [firstpage_image] =>[orig_patent_app_number] => 09680525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680525
Independent reset of arbiters and agents to allow for delayed agent reset Oct 5, 2000 Issued
Array ( [id] => 695175 [patent_doc_number] => 07076586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Default bus grant to a bus agent' [patent_app_type] => utility [patent_app_number] => 09/680757 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9011 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076586.pdf [firstpage_image] =>[orig_patent_app_number] => 09680757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680757
Default bus grant to a bus agent Oct 5, 2000 Issued
Array ( [id] => 1007675 [patent_doc_number] => 06907486 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Disk module of solid state' [patent_app_type] => utility [patent_app_number] => 09/679544 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1594 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907486.pdf [firstpage_image] =>[orig_patent_app_number] => 09679544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679544
Disk module of solid state Oct 5, 2000 Issued
Array ( [id] => 7633111 [patent_doc_number] => 06658509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Multi-tier point-to-point ring memory interface' [patent_app_type] => B1 [patent_app_number] => 09/678638 [patent_app_country] => US [patent_app_date] => 2000-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6351 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658509.pdf [firstpage_image] =>[orig_patent_app_number] => 09678638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/678638
Multi-tier point-to-point ring memory interface Oct 2, 2000 Issued
Array ( [id] => 1186308 [patent_doc_number] => 06742065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Interrupt controller and method of accessing interrupts' [patent_app_type] => B1 [patent_app_number] => 09/676113 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3277 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742065.pdf [firstpage_image] =>[orig_patent_app_number] => 09676113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676113
Interrupt controller and method of accessing interrupts Sep 28, 2000 Issued
Array ( [id] => 7615426 [patent_doc_number] => 06948020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Method and system for increasing control information from GPIOs' [patent_app_type] => utility [patent_app_number] => 09/677314 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1470 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948020.pdf [firstpage_image] =>[orig_patent_app_number] => 09677314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677314
Method and system for increasing control information from GPIOs Sep 28, 2000 Issued
Array ( [id] => 7628199 [patent_doc_number] => 06820161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects' [patent_app_type] => B1 [patent_app_number] => 09/671065 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4462 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820161.pdf [firstpage_image] =>[orig_patent_app_number] => 09671065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671065
Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects Sep 27, 2000 Issued
Array ( [id] => 1236195 [patent_doc_number] => 06694390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Managing bus transaction dependencies' [patent_app_type] => B1 [patent_app_number] => 09/659108 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3113 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694390.pdf [firstpage_image] =>[orig_patent_app_number] => 09659108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659108
Managing bus transaction dependencies Sep 10, 2000 Issued
Array ( [id] => 1200894 [patent_doc_number] => 06728809 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Time-out control apparatus, terminal unit, time-out control system and time-out procedure' [patent_app_type] => B1 [patent_app_number] => 09/658005 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 6643 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728809.pdf [firstpage_image] =>[orig_patent_app_number] => 09658005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658005
Time-out control apparatus, terminal unit, time-out control system and time-out procedure Sep 7, 2000 Issued
Array ( [id] => 1284347 [patent_doc_number] => 06651121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method and apparatus for facilitating scalability during automated data processing' [patent_app_type] => B1 [patent_app_number] => 09/658240 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 26787 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651121.pdf [firstpage_image] =>[orig_patent_app_number] => 09658240 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658240
Method and apparatus for facilitating scalability during automated data processing Sep 7, 2000 Issued
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