
Dhaval V. Patel
Examiner (ID: 4462, Phone: (571)270-1818 , Office: P/2631 )
| Most Active Art Unit | 2631 |
| Art Unit(s) | 2611, 2631 |
| Total Applications | 1587 |
| Issued Applications | 1334 |
| Pending Applications | 84 |
| Abandoned Applications | 204 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1471891
[patent_doc_number] => 06460107
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Integrated real-time performance monitoring facility'
[patent_app_type] => B1
[patent_app_number] => 09/301870
[patent_app_country] => US
[patent_app_date] => 1999-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 5022
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/460/06460107.pdf
[firstpage_image] =>[orig_patent_app_number] => 09301870
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/301870 | Integrated real-time performance monitoring facility | Apr 28, 1999 | Issued |
Array
(
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[patent_doc_number] => 06449670
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[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Microcomputer with bit packets for interrupts, control and memory access'
[patent_app_type] => B1
[patent_app_number] => 09/301495
[patent_app_country] => US
[patent_app_date] => 1999-04-28
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[pdf_file] => patents/06/449/06449670.pdf
[firstpage_image] =>[orig_patent_app_number] => 09301495
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/301495 | Microcomputer with bit packets for interrupts, control and memory access | Apr 27, 1999 | Issued |
Array
(
[id] => 1178762
[patent_doc_number] => 06757759
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-29
[patent_title] => 'Microcomputer chips with interconnected address and data paths'
[patent_app_type] => B1
[patent_app_number] => 09/301487
[patent_app_country] => US
[patent_app_date] => 1999-04-28
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[pdf_file] => patents/06/757/06757759.pdf
[firstpage_image] =>[orig_patent_app_number] => 09301487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/301487 | Microcomputer chips with interconnected address and data paths | Apr 27, 1999 | Issued |
Array
(
[id] => 1311097
[patent_doc_number] => 06625679
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Apparatus and method for converting interrupt transactions to interrupt signals to distribute interrupts to IA-32 processors'
[patent_app_type] => B1
[patent_app_number] => 09/294927
[patent_app_country] => US
[patent_app_date] => 1999-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/06/625/06625679.pdf
[firstpage_image] =>[orig_patent_app_number] => 09294927
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/294927 | Apparatus and method for converting interrupt transactions to interrupt signals to distribute interrupts to IA-32 processors | Apr 18, 1999 | Issued |
Array
(
[id] => 7645912
[patent_doc_number] => 06477611
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Field-configurable, adaptable and programmable input/output bus interface and method'
[patent_app_type] => B1
[patent_app_number] => 09/293253
[patent_app_country] => US
[patent_app_date] => 1999-04-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/477/06477611.pdf
[firstpage_image] =>[orig_patent_app_number] => 09293253
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/293253 | Field-configurable, adaptable and programmable input/output bus interface and method | Apr 15, 1999 | Issued |
Array
(
[id] => 1539095
[patent_doc_number] => 06412034
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Transaction-based locking approach'
[patent_app_type] => B1
[patent_app_number] => 09/293360
[patent_app_country] => US
[patent_app_date] => 1999-04-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/412/06412034.pdf
[firstpage_image] =>[orig_patent_app_number] => 09293360
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/293360 | Transaction-based locking approach | Apr 15, 1999 | Issued |
| 09/283334 | SUSPENDING TO NONVOLATILE STORAGE | Mar 30, 1999 | Abandoned |
Array
(
[id] => 1456656
[patent_doc_number] => 06457082
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[patent_issue_date] => 2002-09-24
[patent_title] => 'Break event generation during transitions between modes of operation in a computer system'
[patent_app_type] => B1
[patent_app_number] => 09/281366
[patent_app_country] => US
[patent_app_date] => 1999-03-30
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[pdf_file] => patents/06/457/06457082.pdf
[firstpage_image] =>[orig_patent_app_number] => 09281366
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/281366 | Break event generation during transitions between modes of operation in a computer system | Mar 29, 1999 | Issued |
Array
(
[id] => 1584693
[patent_doc_number] => 06449676
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Hot-pluggable voltage regulator module'
[patent_app_type] => B1
[patent_app_number] => 09/281081
[patent_app_country] => US
[patent_app_date] => 1999-03-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/449/06449676.pdf
[firstpage_image] =>[orig_patent_app_number] => 09281081
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/281081 | Hot-pluggable voltage regulator module | Mar 29, 1999 | Issued |
Array
(
[id] => 1311118
[patent_doc_number] => 06625681
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[patent_issue_date] => 2003-09-23
[patent_title] => 'State activated one shot with extended pulse timing for hot-swap applications'
[patent_app_type] => B1
[patent_app_number] => 09/272798
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[pdf_file] => patents/06/625/06625681.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/272798 | State activated one shot with extended pulse timing for hot-swap applications | Mar 28, 1999 | Issued |
Array
(
[id] => 1567381
[patent_doc_number] => 06363452
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Method and apparatus for adding and removing components without powering down computer system'
[patent_app_type] => B1
[patent_app_number] => 09/280784
[patent_app_country] => US
[patent_app_date] => 1999-03-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/363/06363452.pdf
[firstpage_image] =>[orig_patent_app_number] => 09280784
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/280784 | Method and apparatus for adding and removing components without powering down computer system | Mar 28, 1999 | Issued |
Array
(
[id] => 1495202
[patent_doc_number] => 06418490
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[patent_issue_date] => 2002-07-09
[patent_title] => 'Electronic circuit interconnection system using a virtual mirror cross over package'
[patent_app_type] => B1
[patent_app_number] => 09/280025
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[pdf_file] => patents/06/418/06418490.pdf
[firstpage_image] =>[orig_patent_app_number] => 09280025
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/280025 | Electronic circuit interconnection system using a virtual mirror cross over package | Mar 25, 1999 | Issued |
Array
(
[id] => 7645934
[patent_doc_number] => 06477589
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[patent_issue_date] => 2002-11-05
[patent_title] => 'Information processing apparatus and method'
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[patent_app_number] => 09/270210
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[firstpage_image] =>[orig_patent_app_number] => 09270210
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/270210 | Information processing apparatus and method | Mar 14, 1999 | Issued |
Array
(
[id] => 7622396
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[patent_title] => 'Controlling consumption of time-stamped information by a buffered system'
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Array
(
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Array
(
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Array
(
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[patent_title] => 'Chip with debug capability'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/241204 | Chip with debug capability | Jan 31, 1999 | Issued |
Array
(
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Array
(
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Array
(
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