Search

Dhaval V. Patel

Examiner (ID: 4462, Phone: (571)270-1818 , Office: P/2631 )

Most Active Art Unit
2631
Art Unit(s)
2611, 2631
Total Applications
1587
Issued Applications
1334
Pending Applications
84
Abandoned Applications
204

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1539104 [patent_doc_number] => 06412036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Apparatus for testing input/output interface of computer system' [patent_app_type] => B1 [patent_app_number] => 09/220553 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1519 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412036.pdf [firstpage_image] =>[orig_patent_app_number] => 09220553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/220553
Apparatus for testing input/output interface of computer system Dec 22, 1998 Issued
Array ( [id] => 695188 [patent_doc_number] => 07076592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Power node control center' [patent_app_type] => utility [patent_app_number] => 09/213099 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 10647 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076592.pdf [firstpage_image] =>[orig_patent_app_number] => 09213099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213099
Power node control center Dec 16, 1998 Issued
Array ( [id] => 1475124 [patent_doc_number] => 06408405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'System and method for displaying and analyzing retrieved magnetic tape statistics' [patent_app_type] => B1 [patent_app_number] => 09/209983 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8743 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408405.pdf [firstpage_image] =>[orig_patent_app_number] => 09209983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209983
System and method for displaying and analyzing retrieved magnetic tape statistics Dec 9, 1998 Issued
Array ( [id] => 1460180 [patent_doc_number] => 06463552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Scripting method and apparatus for testing devices' [patent_app_type] => B1 [patent_app_number] => 09/206448 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 20402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463552.pdf [firstpage_image] =>[orig_patent_app_number] => 09206448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206448
Scripting method and apparatus for testing devices Dec 6, 1998 Issued
Array ( [id] => 1585014 [patent_doc_number] => 06449733 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'On-line replacement of process pairs in a clustered processor architecture' [patent_app_type] => B1 [patent_app_number] => 09/206504 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6582 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449733.pdf [firstpage_image] =>[orig_patent_app_number] => 09206504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206504
On-line replacement of process pairs in a clustered processor architecture Dec 6, 1998 Issued
Array ( [id] => 1462510 [patent_doc_number] => 06427213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Apparatus, method and system for file synchronization for a fault tolerate network' [patent_app_type] => B1 [patent_app_number] => 09/193084 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3890 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427213.pdf [firstpage_image] =>[orig_patent_app_number] => 09193084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193084
Apparatus, method and system for file synchronization for a fault tolerate network Nov 15, 1998 Issued
Array ( [id] => 1475111 [patent_doc_number] => 06408401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Embedded RAM with self-test and self-repair with spare rows and columns' [patent_app_type] => B1 [patent_app_number] => 09/191679 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7933 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408401.pdf [firstpage_image] =>[orig_patent_app_number] => 09191679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191679
Embedded RAM with self-test and self-repair with spare rows and columns Nov 12, 1998 Issued
Array ( [id] => 4347095 [patent_doc_number] => 06330687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'System and method to maintain performance among N single raid systems during non-fault conditions while sharing multiple storage devices during conditions of a faulty host computer or faulty storage array controller' [patent_app_type] => 1 [patent_app_number] => 9/192016 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5685 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330687.pdf [firstpage_image] =>[orig_patent_app_number] => 192016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192016
System and method to maintain performance among N single raid systems during non-fault conditions while sharing multiple storage devices during conditions of a faulty host computer or faulty storage array controller Nov 12, 1998 Issued
Array ( [id] => 1462497 [patent_doc_number] => 06427212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Data fault tolerance software apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/191943 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2826 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427212.pdf [firstpage_image] =>[orig_patent_app_number] => 09191943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191943
Data fault tolerance software apparatus and method Nov 12, 1998 Issued
Array ( [id] => 1513448 [patent_doc_number] => 06442715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Look-ahead reallocation disk drive defect management' [patent_app_type] => B1 [patent_app_number] => 09/187061 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10943 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442715.pdf [firstpage_image] =>[orig_patent_app_number] => 09187061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187061
Look-ahead reallocation disk drive defect management Nov 4, 1998 Issued
Array ( [id] => 5861382 [patent_doc_number] => 20020124195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'METHOD AND APPARATUS FOR POWER MANAGEMENT IN A MEMORY SUBSYSTEM' [patent_app_type] => new [patent_app_number] => 09/187565 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3445 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124195.pdf [firstpage_image] =>[orig_patent_app_number] => 09187565 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187565
Method and apparatus for power management in a memory subsystem Nov 3, 1998 Issued
Array ( [id] => 4400870 [patent_doc_number] => 06304981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Adaptive shutdown system and method for an information handling system' [patent_app_type] => 1 [patent_app_number] => 9/174712 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4777 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304981.pdf [firstpage_image] =>[orig_patent_app_number] => 174712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174712
Adaptive shutdown system and method for an information handling system Oct 18, 1998 Issued
Array ( [id] => 4203896 [patent_doc_number] => 06151653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'USB/UART converter and its control method' [patent_app_type] => 1 [patent_app_number] => 9/175150 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3351 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151653.pdf [firstpage_image] =>[orig_patent_app_number] => 175150 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175150
USB/UART converter and its control method Oct 18, 1998 Issued
Array ( [id] => 1549511 [patent_doc_number] => 06374318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Filter-circuit for computer system bus' [patent_app_type] => B1 [patent_app_number] => 09/174275 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6053 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374318.pdf [firstpage_image] =>[orig_patent_app_number] => 09174275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174275
Filter-circuit for computer system bus Oct 15, 1998 Issued
Array ( [id] => 1567655 [patent_doc_number] => 06438712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Quick identification of defect-uncovering files' [patent_app_type] => B1 [patent_app_number] => 09/169210 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5412 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438712.pdf [firstpage_image] =>[orig_patent_app_number] => 09169210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169210
Quick identification of defect-uncovering files Oct 8, 1998 Issued
Array ( [id] => 1225857 [patent_doc_number] => 06704875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method of operation controller having processor for controlling industrial machine' [patent_app_type] => B1 [patent_app_number] => 09/155827 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3976 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704875.pdf [firstpage_image] =>[orig_patent_app_number] => 09155827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/155827
Method of operation controller having processor for controlling industrial machine Oct 5, 1998 Issued
Array ( [id] => 4312722 [patent_doc_number] => 06237103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Power sequencing in a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/163512 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2088 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237103.pdf [firstpage_image] =>[orig_patent_app_number] => 163512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163512
Power sequencing in a data processing system Sep 29, 1998 Issued
09/163271 UPGRADE CARD FOR A COMPUTER SYSTEM Sep 28, 1998 Abandoned
Array ( [id] => 1604467 [patent_doc_number] => 06434653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus for disabling power-on in a system requiring add-in modules' [patent_app_type] => B1 [patent_app_number] => 09/163291 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5098 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434653.pdf [firstpage_image] =>[orig_patent_app_number] => 09163291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163291
Method and apparatus for disabling power-on in a system requiring add-in modules Sep 28, 1998 Issued
Array ( [id] => 4111103 [patent_doc_number] => 06134701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Computer motherboard with a control chip having specific pin arrangement for fast cache access' [patent_app_type] => 1 [patent_app_number] => 9/159441 [patent_app_country] => US [patent_app_date] => 1998-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134701.pdf [firstpage_image] =>[orig_patent_app_number] => 159441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159441
Computer motherboard with a control chip having specific pin arrangement for fast cache access Sep 21, 1998 Issued
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