Dhirubhai R Patel
Examiner (ID: 9466, Phone: (571)272-1983 , Office: P/2848 )
Most Active Art Unit | 2831 |
Art Unit(s) | 2109, 2848, 2831, 2835 |
Total Applications | 2537 |
Issued Applications | 2230 |
Pending Applications | 45 |
Abandoned Applications | 262 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10210595
[patent_doc_number] => 20150095586
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[patent_title] => 'STORING NON-TEMPORAL CACHE DATA'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2013-09-30
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Array
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[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'STORAGE SYSTEM AND STORAGE DEVICE CONFIGURATION REPORTING'
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Array
(
[id] => 13186041
[patent_doc_number] => 10108540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-23
[patent_title] => Allocation of distributed data structures
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2014-02-20
[patent_title] => 'SYSTEM CONTROLLING APPARATUS, INFORMATION PROCESSING SYSTEM, AND CONTROLLING METHOD OF SYSTEM CONTROLLING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/916630
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Array
(
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[patent_title] => 'READING VOLTAGE CALCULATION IN SOLID-STATE STORAGE DEVICES'
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Array
(
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[patent_issue_date] => 2014-12-18
[patent_title] => 'ALLOCATION OF DISTRIBUTED DATA STRUCTURES'
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Array
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Array
(
[id] => 11769479
[patent_doc_number] => 09378143
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[patent_kind] => B2
[patent_issue_date] => 2016-06-28
[patent_title] => 'Managing transactional and non-transactional store observability'
[patent_app_type] => utility
[patent_app_number] => 13/788200
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Array
(
[id] => 10524577
[patent_doc_number] => 09251092
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[patent_issue_date] => 2016-02-02
[patent_title] => 'Hybrid address translation'
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Array
(
[id] => 13083111
[patent_doc_number] => 10061622
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[patent_kind] => B2
[patent_issue_date] => 2018-08-28
[patent_title] => Updating memory topology information for virtual machines
[patent_app_type] => utility
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Array
(
[id] => 9688132
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[patent_title] => 'Metadata Update Management In a Multi-Tiered Memory'
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Array
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Array
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Array
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Array
(
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/670009 | Configurable I/O address translation data structure | Nov 5, 2012 | Issued |