
Diana Cheng
Examiner (ID: 1053, Phone: (571)270-1197 , Office: P/2842 )
| Most Active Art Unit | 2849 |
| Art Unit(s) | 2849, 2816, 2842, 2892 |
| Total Applications | 1059 |
| Issued Applications | 859 |
| Pending Applications | 71 |
| Abandoned Applications | 157 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17417799
[patent_doc_number] => 20220052703
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-17
[patent_title] => SIGNAL GENERATION CIRCUIT AND METHOD, AND DIGIT-TO-TIME CONVERSION CIRCUIT AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/296305
[patent_app_country] => US
[patent_app_date] => 2020-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21969
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296305
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/296305 | Signal generation circuit and method, and digit-to-time conversion circuit and method | Aug 9, 2020 | Issued |
Array
(
[id] => 17812675
[patent_doc_number] => 20220264510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => WEARABLE DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/627218
[patent_app_country] => US
[patent_app_date] => 2020-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17627218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/627218 | Wearable device and method | Aug 5, 2020 | Issued |
Array
(
[id] => 17812675
[patent_doc_number] => 20220264510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => WEARABLE DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/627218
[patent_app_country] => US
[patent_app_date] => 2020-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17627218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/627218 | Wearable device and method | Aug 5, 2020 | Issued |
Array
(
[id] => 17364722
[patent_doc_number] => 11231743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-25
[patent_title] => Timer, electronic apparatus, and vehicle
[patent_app_type] => utility
[patent_app_number] => 16/937757
[patent_app_country] => US
[patent_app_date] => 2020-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 13673
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937757
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/937757 | Timer, electronic apparatus, and vehicle | Jul 23, 2020 | Issued |
Array
(
[id] => 16654088
[patent_doc_number] => 10931286
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-23
[patent_title] => Field programmable gate array with external phase-locked loop
[patent_app_type] => utility
[patent_app_number] => 16/937314
[patent_app_country] => US
[patent_app_date] => 2020-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 31
[patent_no_of_words] => 15949
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 606
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937314
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/937314 | Field programmable gate array with external phase-locked loop | Jul 22, 2020 | Issued |
Array
(
[id] => 16944768
[patent_doc_number] => 11057027
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-06
[patent_title] => Circuit having a plurality of modes
[patent_app_type] => utility
[patent_app_number] => 16/935158
[patent_app_country] => US
[patent_app_date] => 2020-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1786
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935158
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/935158 | Circuit having a plurality of modes | Jul 20, 2020 | Issued |
Array
(
[id] => 16835717
[patent_doc_number] => 11011979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-18
[patent_title] => Booster circuit
[patent_app_type] => utility
[patent_app_number] => 16/930983
[patent_app_country] => US
[patent_app_date] => 2020-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2796
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930983
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/930983 | Booster circuit | Jul 15, 2020 | Issued |
Array
(
[id] => 17994230
[patent_doc_number] => 20220360267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => PHASE-LOCKED LOOP CIRCUIT, CONFIGURATION METHOD THEREFOR, AND COMMUNICATION APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/624063
[patent_app_country] => US
[patent_app_date] => 2020-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8890
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17624063
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/624063 | Phase-locked loop circuit, configuration method therefor, and communication apparatus | Jun 18, 2020 | Issued |
Array
(
[id] => 17211254
[patent_doc_number] => 11171643
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-11-09
[patent_title] => SiC gate drive control with trench FETs from high dV\dT at drain source
[patent_app_type] => utility
[patent_app_number] => 16/887600
[patent_app_country] => US
[patent_app_date] => 2020-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5359
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887600
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/887600 | SiC gate drive control with trench FETs from high dVdT at drain source | May 28, 2020 | Issued |
Array
(
[id] => 17019072
[patent_doc_number] => 11088726
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-10
[patent_title] => Device and method for NFC device charging
[patent_app_type] => utility
[patent_app_number] => 16/879314
[patent_app_country] => US
[patent_app_date] => 2020-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6606
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879314
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/879314 | Device and method for NFC device charging | May 19, 2020 | Issued |
Array
(
[id] => 17739809
[patent_doc_number] => 20220225271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => METHODS FOR ENABLING DOWNLINK DATA COMMUNICATION BETWEEN A WIRELESS DEVICE AND A NETWORK NODE, WIRELESS DEVICES AND NETWORK NODES
[patent_app_type] => utility
[patent_app_number] => 17/613052
[patent_app_country] => US
[patent_app_date] => 2020-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7493
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17613052
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/613052 | METHODS FOR ENABLING DOWNLINK DATA COMMUNICATION BETWEEN A WIRELESS DEVICE AND A NETWORK NODE, WIRELESS DEVICES AND NETWORK NODES | May 14, 2020 | Abandoned |
Array
(
[id] => 16509870
[patent_doc_number] => 20200389126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-10
[patent_title] => EFFICIENT HIGH POWER MICROWAVE GENERATION USING RECIRCULATING PULSES
[patent_app_type] => utility
[patent_app_number] => 16/856219
[patent_app_country] => US
[patent_app_date] => 2020-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9681
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856219
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/856219 | Efficient high power microwave generation using recirculating pulses | Apr 22, 2020 | Issued |
Array
(
[id] => 20275037
[patent_doc_number] => 12444824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Resonator apparatus, filter apparatus as well as radio frequency and microwave device
[patent_app_type] => utility
[patent_app_number] => 17/623063
[patent_app_country] => US
[patent_app_date] => 2020-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 2262
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623063
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/623063 | Resonator apparatus, filter apparatus as well as radio frequency and microwave device | Apr 16, 2020 | Issued |
Array
(
[id] => 16365139
[patent_doc_number] => 20200321890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-08
[patent_title] => METHOD AND HALF BRIDGE CONTROLLER FOR DETERMINING A POLARITY OF A HALF BRIDGE CURRENT
[patent_app_type] => utility
[patent_app_number] => 16/841066
[patent_app_country] => US
[patent_app_date] => 2020-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7698
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841066
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/841066 | Method and half bridge controller for determining a polarity of a half bridge current | Apr 5, 2020 | Issued |
Array
(
[id] => 17113776
[patent_doc_number] => 20210294373
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => WORKLOAD BASED ADAPTIVE VOLTAGE AND FREQUENCY CONTROL APPARATUS AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/823221
[patent_app_country] => US
[patent_app_date] => 2020-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10023
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823221
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/823221 | Workload based adaptive voltage and frequency control apparatus and method | Mar 17, 2020 | Issued |
Array
(
[id] => 17268936
[patent_doc_number] => 11194359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-07
[patent_title] => Clock monitoring circuit and integrated circuit including the same
[patent_app_type] => utility
[patent_app_number] => 16/815503
[patent_app_country] => US
[patent_app_date] => 2020-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12049
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815503
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/815503 | Clock monitoring circuit and integrated circuit including the same | Mar 10, 2020 | Issued |
Array
(
[id] => 16789858
[patent_doc_number] => 10992301
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-04-27
[patent_title] => Circuit and method for generating temperature-stable clocks using ordinary oscillators
[patent_app_type] => utility
[patent_app_number] => 16/816113
[patent_app_country] => US
[patent_app_date] => 2020-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5047
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816113
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/816113 | Circuit and method for generating temperature-stable clocks using ordinary oscillators | Mar 10, 2020 | Issued |
Array
(
[id] => 16739619
[patent_doc_number] => 10965293
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-30
[patent_title] => Voltage controlled delay line gain calibration
[patent_app_type] => utility
[patent_app_number] => 16/810225
[patent_app_country] => US
[patent_app_date] => 2020-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 4501
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810225
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/810225 | Voltage controlled delay line gain calibration | Mar 4, 2020 | Issued |
Array
(
[id] => 16586869
[patent_doc_number] => 20210021271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-21
[patent_title] => PHASE-LOCKED LOOP CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/808559
[patent_app_country] => US
[patent_app_date] => 2020-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5148
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 346
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808559
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/808559 | Phase-locked loop circuit | Mar 3, 2020 | Issued |
Array
(
[id] => 16774772
[patent_doc_number] => 10985900
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-04-20
[patent_title] => Estimating clock phase error based on channel conditions
[patent_app_type] => utility
[patent_app_number] => 16/807356
[patent_app_country] => US
[patent_app_date] => 2020-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6010
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807356
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/807356 | Estimating clock phase error based on channel conditions | Mar 2, 2020 | Issued |