Search

Diana Cheng

Examiner (ID: 15822, Phone: (571)270-1197 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2816, 2836, 2892, 2842, 2849
Total Applications
1074
Issued Applications
880
Pending Applications
54
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11631382 [patent_doc_number] => 20170141571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'MIXED SIGNAL CONTROLLER' [patent_app_type] => utility [patent_app_number] => 15/218070 [patent_app_country] => US [patent_app_date] => 2016-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15218070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/218070
Mixed signal controller Jul 23, 2016 Issued
Array ( [id] => 12155349 [patent_doc_number] => 20180026613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'BALANCING DELAY ASSOCIATED WITH DUAL-EDGE TRIGGER CLOCK GATERS' [patent_app_type] => utility [patent_app_number] => 15/217122 [patent_app_country] => US [patent_app_date] => 2016-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15217122 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/217122
Balancing delay associated with dual-edge trigger clock gaters Jul 21, 2016 Issued
Array ( [id] => 11823604 [patent_doc_number] => 20170212540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'LOW DROPOUT VOLTAGE (LDO) REGULATOR INCLUDING A DUAL LOOP CIRCUIT AND AN APPLICATION PROCESSOR AND A USER DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/216147 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11246 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15216147 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/216147
Low dropout voltage (LDO) regulator including a dual loop circuit and an application processor and a user device including the same Jul 20, 2016 Issued
Array ( [id] => 12155367 [patent_doc_number] => 20180026632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'ULTRA-LOW POWER CROSS-POINT ELECTRONIC SWITCH APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/213541 [patent_app_country] => US [patent_app_date] => 2016-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15213541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/213541
Ultra-low power cross-point electronic switch apparatus and method Jul 18, 2016 Issued
Array ( [id] => 12141652 [patent_doc_number] => 20180019735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SYSTEMS AND METHODS FOR NON-VOLATILE FLIP FLOPS' [patent_app_type] => utility [patent_app_number] => 15/212826 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7229 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212826
Systems and methods for non-volatile flip flops Jul 17, 2016 Issued
Array ( [id] => 11623819 [patent_doc_number] => 20170134008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'MIXED-TECHNOLOGY COMBINATION OF PROGRAMMABLE ELEMENTS' [patent_app_type] => utility [patent_app_number] => 15/212094 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212094 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212094
Mixed-technology combination of programmable elements Jul 14, 2016 Issued
Array ( [id] => 12139899 [patent_doc_number] => 20180017981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'APPARATUS, SYSTEMS AND METHODS FOR GENERATING VOLTAGE EXCITATION WAVEFORMS' [patent_app_type] => utility [patent_app_number] => 15/210498 [patent_app_country] => US [patent_app_date] => 2016-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8202 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15210498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/210498
Apparatus, systems and methods for generating voltage excitation waveforms Jul 13, 2016 Issued
Array ( [id] => 12955519 [patent_doc_number] => 09838003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Correcting high voltage source follower level shift [patent_app_type] => utility [patent_app_number] => 15/210672 [patent_app_country] => US [patent_app_date] => 2016-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15210672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/210672
Correcting high voltage source follower level shift Jul 13, 2016 Issued
Array ( [id] => 11525229 [patent_doc_number] => 09608648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Wideband direct modulation with two-point injection in digital phase locked loops' [patent_app_type] => utility [patent_app_number] => 15/207266 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15207266 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/207266
Wideband direct modulation with two-point injection in digital phase locked loops Jul 10, 2016 Issued
Array ( [id] => 11118629 [patent_doc_number] => 20160315603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'Method And System For Cancellation Of Spurious Signals' [patent_app_type] => utility [patent_app_number] => 15/202215 [patent_app_country] => US [patent_app_date] => 2016-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6047 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202215 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202215
Method and system for cancellation of spurious signals Jul 4, 2016 Issued
Array ( [id] => 12257570 [patent_doc_number] => 09929727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'System and method for a switching transistor' [patent_app_type] => utility [patent_app_number] => 15/190874 [patent_app_country] => US [patent_app_date] => 2016-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7111 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15190874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/190874
System and method for a switching transistor Jun 22, 2016 Issued
Array ( [id] => 11525227 [patent_doc_number] => 09608646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'PLL circuit and operation method' [patent_app_type] => utility [patent_app_number] => 15/178775 [patent_app_country] => US [patent_app_date] => 2016-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8215 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178775 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178775
PLL circuit and operation method Jun 9, 2016 Issued
Array ( [id] => 11386565 [patent_doc_number] => 20170012622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'COMMUNICATING ACROSS GALVANIC ISOLATION, FOR EXAMPLE, IN A POWER CONVERTER' [patent_app_type] => utility [patent_app_number] => 15/179871 [patent_app_country] => US [patent_app_date] => 2016-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17431 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15179871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/179871
Communicating across galvanic isolation, for example, in a power converter Jun 9, 2016 Issued
Array ( [id] => 12229639 [patent_doc_number] => 09916886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Circuit for generating periodic signal and memory device including same' [patent_app_type] => utility [patent_app_number] => 15/177214 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9093 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177214
Circuit for generating periodic signal and memory device including same Jun 7, 2016 Issued
Array ( [id] => 12096092 [patent_doc_number] => 20170353185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'TRANSMITTER WITH FEEDBACK TERMINATED PREEMPHASIS' [patent_app_type] => utility [patent_app_number] => 15/174842 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174842 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174842
Transmitter with feedback terminated preemphasis Jun 5, 2016 Issued
Array ( [id] => 11891547 [patent_doc_number] => 09762120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Circuit for clamping current in a charge pump' [patent_app_type] => utility [patent_app_number] => 15/174050 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10176 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174050
Circuit for clamping current in a charge pump Jun 5, 2016 Issued
Array ( [id] => 11328868 [patent_doc_number] => 20160359480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'APPARATUS FOR DRIVING INSULATED GATE BIPOLAR TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/172003 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3020 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/172003
APPARATUS FOR DRIVING INSULATED GATE BIPOLAR TRANSISTOR Jun 1, 2016 Abandoned
Array ( [id] => 12316503 [patent_doc_number] => 09941891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Adaptive spur cancellation techniques and multi-phase injection locked TDC for digital phase locked loop circuit [patent_app_type] => utility [patent_app_number] => 15/170882 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 7139 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170882 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170882
Adaptive spur cancellation techniques and multi-phase injection locked TDC for digital phase locked loop circuit May 31, 2016 Issued
Array ( [id] => 11354382 [patent_doc_number] => 20160373122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'FREQUENCY SYNTHESIZER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/170624 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4414 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170624
FREQUENCY SYNTHESIZER CIRCUIT May 31, 2016 Abandoned
Array ( [id] => 11862677 [patent_doc_number] => 09742380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'Phase-locked loop having sampling phase detector' [patent_app_type] => utility [patent_app_number] => 15/170797 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170797 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170797
Phase-locked loop having sampling phase detector May 31, 2016 Issued
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