Diana Cheng

Array ( [id] => 19758705 [patent_doc_number] => 20250047270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => DELAY CALIBRATION CIRCUIT AND DELAY CALIBRATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/401470 [patent_app_country] => US [patent_app_date] => 2023-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20073020 [patent_doc_number] => 20250211242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => QUANTIZATION EXTRACTION FOR PHASE-LOCKED LOOP OSCILLATORS [patent_app_type] => utility [patent_app_number] => 18/395109 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19965417 [patent_doc_number] => 12334941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Unlimited bandwidth shifting systems and methods of an all-digital phase locked loop [patent_app_type] => utility [patent_app_number] => 18/544289 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19965417 [patent_doc_number] => 12334941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Unlimited bandwidth shifting systems and methods of an all-digital phase locked loop [patent_app_type] => utility [patent_app_number] => 18/544289 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20228284 [patent_doc_number] => 12416934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Radio-frequency switches [patent_app_type] => utility [patent_app_number] => 18/529251 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 2884 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20228284 [patent_doc_number] => 12416934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Radio-frequency switches [patent_app_type] => utility [patent_app_number] => 18/529251 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 2884 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20346489 [patent_doc_number] => 12470225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Fractional frequency synthesizer utilizing multi-phase divider circuitry [patent_app_type] => utility [patent_app_number] => 18/526670 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19727676 [patent_doc_number] => 20250030427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => CIRCUIT WITH A PHASE LOCKED LOOP WITH DISTURBANCE RESPONSES [patent_app_type] => utility [patent_app_number] => 18/524711 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19912879 [patent_doc_number] => 12289105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Electronic device, operating method thereof, and electronic system [patent_app_type] => utility [patent_app_number] => 18/514975 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19039063 [patent_doc_number] => 20240088878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => FOLDED RAMP GENERATOR [patent_app_type] => utility [patent_app_number] => 18/512158 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19039063 [patent_doc_number] => 20240088878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => FOLDED RAMP GENERATOR [patent_app_type] => utility [patent_app_number] => 18/512158 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19286713 [patent_doc_number] => 20240223193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => PHASE-LOCKED LOOP DEVICE [patent_app_type] => utility [patent_app_number] => 18/501024 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20003234 [patent_doc_number] => 20250141456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DIGITAL PHASE-LOCKED LOOPS (PLL) INCLUDING CLOSED-LOOP TIME-TO-DIGITAL CONVERTER (TDC) GAIN CALIBRATION CIRCUITS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/385729 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20003234 [patent_doc_number] => 20250141456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DIGITAL PHASE-LOCKED LOOPS (PLL) INCLUDING CLOSED-LOOP TIME-TO-DIGITAL CONVERTER (TDC) GAIN CALIBRATION CIRCUITS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/385729 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20003233 [patent_doc_number] => 20250141455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DELAY ELEMENT GAIN CALIBRATION [patent_app_type] => utility [patent_app_number] => 18/497464 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20003233 [patent_doc_number] => 20250141455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DELAY ELEMENT GAIN CALIBRATION [patent_app_type] => utility [patent_app_number] => 18/497464 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19867049 [patent_doc_number] => 20250105835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => Output Driving Circuit for Power Devices [patent_app_type] => utility [patent_app_number] => 18/384879 [patent_app_country] => US [patent_app_date] => 2023-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19192254 [patent_doc_number] => 20240171167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => ENHANCEMENT OF LINEARITY FOR DIGITALLY CONTROLLED DELAY LINE [patent_app_type] => utility [patent_app_number] => 18/496495 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18496495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19192254 [patent_doc_number] => 20240171167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => ENHANCEMENT OF LINEARITY FOR DIGITALLY CONTROLLED DELAY LINE [patent_app_type] => utility [patent_app_number] => 18/496495 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18496495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19994541 [patent_doc_number] => 20250132763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => PHASE-LOCKED LOOP UPDATE CANCELLATION [patent_app_type] => utility [patent_app_number] => 18/492453 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492453 [rel_patent_id] =>[rel_patent_doc_number] =>)