Diana Cheng

Array ( [id] => 18548779 [patent_doc_number] => 11722142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-08 [patent_title] => Charge pump with output current adjustment [patent_app_type] => utility [patent_app_number] => 17/849594 [patent_app_country] => US [patent_app_date] => 2022-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19123964 [patent_doc_number] => 11967965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable [patent_app_type] => utility [patent_app_number] => 17/806735 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6409 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19016916 [patent_doc_number] => 11923864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Fast switching of output frequency of a phase locked loop (PLL) [patent_app_type] => utility [patent_app_number] => 17/806736 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4383 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18640160 [patent_doc_number] => 11764792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Phase locked loop circuitry [patent_app_type] => utility [patent_app_number] => 17/837516 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8073 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17837516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18782766 [patent_doc_number] => 11824543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Folded ramp generator [patent_app_type] => utility [patent_app_number] => 17/832280 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7798 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19016912 [patent_doc_number] => 11923860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => PLL circuit [patent_app_type] => utility [patent_app_number] => 17/831788 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9564 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18813583 [patent_doc_number] => 20230387920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => PHASE-LOCKED LOOP CIRCUIT USING HYBRID LOOP CALIBRATION SCHEME AND ADAPTIVELY UPDATED LOOKUP TABLES AND ASSOCIATED CLOCK GENERATING METHOD [patent_app_type] => utility [patent_app_number] => 17/751679 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18098475 [patent_doc_number] => 20220416816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => RADIO FREQUENCY SWITCH CONTROL CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/663889 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18834489 [patent_doc_number] => 20230403016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => Unlimited Bandwidth Shifting Systems and Methods of an All-Digital Phase Locked Loop [patent_app_type] => utility [patent_app_number] => 17/746729 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17983977 [patent_doc_number] => 20220350013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => ELECTRONIC DEVICE FOR TRANSMITTING AND RECEIVING DATA UPON ULTRA WIDE BAND RANGING AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/663351 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18521188 [patent_doc_number] => 11711087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Reducing noise contribution in compensating for unequal successive time periods of a reference clock in a fractional-N phase locked loop [patent_app_type] => utility [patent_app_number] => 17/663217 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6468 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18802823 [patent_doc_number] => 11835980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Methods related to controlling switches [patent_app_type] => utility [patent_app_number] => 17/741376 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 8150 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18849748 [patent_doc_number] => 20230412152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SYSTEM AND METHOD FOR REDUCING CIRCUIT ELEMENTS IN HIGH-PERFORMANCE FLIP-FLOPS [patent_app_type] => utility [patent_app_number] => 17/739136 [patent_app_country] => US [patent_app_date] => 2022-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17842126 [patent_doc_number] => 20220279432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Communication Method, Communications Apparatus, and Communications System [patent_app_type] => utility [patent_app_number] => 17/662120 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20190234 [patent_doc_number] => 12401365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Device and method for detecting a harmonic state [patent_app_type] => utility [patent_app_number] => 18/558385 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18558385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168957 [patent_doc_number] => 11984876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Temperature-sensitive sampling [patent_app_type] => utility [patent_app_number] => 17/732986 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6744 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18279821 [patent_doc_number] => 20230095293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => ADJUSTABLE PHASE LOCKED LOOP [patent_app_type] => utility [patent_app_number] => 17/730205 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19222300 [patent_doc_number] => 20240187004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DIGITAL CLEAN UP OSCILLATOR [patent_app_type] => utility [patent_app_number] => 18/287746 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18287746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18670557 [patent_doc_number] => 11777474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Signal generation circuit having minimum delay, semiconductor apparatus using the same, and signal generation method [patent_app_type] => utility [patent_app_number] => 17/725904 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14925 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18175655 [patent_doc_number] => 11575381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-07 [patent_title] => Field programmable gate array with external phase-locked loop [patent_app_type] => utility [patent_app_number] => 17/723145 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 16028 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723145 [rel_patent_id] =>[rel_patent_doc_number] =>)