Search

Diana Cheng

Examiner (ID: 17235, Phone: (571)270-1197 , Office: P/2842 )

Most Active Art Unit
2849
Art Unit(s)
2816, 2892, 2842, 2849
Total Applications
1064
Issued Applications
866
Pending Applications
66
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17971888 [patent_doc_number] => 11489443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Charge pump circuit [patent_app_type] => utility [patent_app_number] => 17/445598 [patent_app_country] => US [patent_app_date] => 2021-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3262 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445598
Charge pump circuit Aug 20, 2021 Issued
Array ( [id] => 18001576 [patent_doc_number] => 11502694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Field programmable gate array with external phase-locked loop [patent_app_type] => utility [patent_app_number] => 17/405188 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 16007 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 562 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405188 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405188
Field programmable gate array with external phase-locked loop Aug 17, 2021 Issued
Array ( [id] => 17390255 [patent_doc_number] => 20220038107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => FAST BANDWIDTH SPECTRUM ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/403763 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403763 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403763
Fast bandwidth spectrum analysis Aug 15, 2021 Issued
Array ( [id] => 17819120 [patent_doc_number] => 11424748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-23 [patent_title] => Modified PID loop filter to suppress high frequency noise in digital phase locked loop [patent_app_type] => utility [patent_app_number] => 17/398228 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10399 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398228 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398228
Modified PID loop filter to suppress high frequency noise in digital phase locked loop Aug 9, 2021 Issued
Array ( [id] => 17758524 [patent_doc_number] => 11398827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Phase-locked loop with phase noise cancellation [patent_app_type] => utility [patent_app_number] => 17/444636 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5260 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17444636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/444636
Phase-locked loop with phase noise cancellation Aug 5, 2021 Issued
Array ( [id] => 17390254 [patent_doc_number] => 20220038106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => DIGITAL LOOP FILTER IN ALL-DIGITAL PHASE-LOCKED LOOP [patent_app_type] => utility [patent_app_number] => 17/389663 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389663 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389663
Digital loop filter in all-digital phase-locked loop Jul 29, 2021 Issued
Array ( [id] => 17390252 [patent_doc_number] => 20220038104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => ALL-DIGITAL PHASE-LOCKED LOOP [patent_app_type] => utility [patent_app_number] => 17/389698 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389698
All-digital phase-locked loop Jul 29, 2021 Issued
Array ( [id] => 18508080 [patent_doc_number] => 11705912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Digital phase locked loop tracking [patent_app_type] => utility [patent_app_number] => 17/386774 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386774 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386774
Digital phase locked loop tracking Jul 27, 2021 Issued
Array ( [id] => 18052756 [patent_doc_number] => 11526136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Time-to-digital conversion circuit and source driver including the same [patent_app_type] => utility [patent_app_number] => 17/443799 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5801 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443799
Time-to-digital conversion circuit and source driver including the same Jul 26, 2021 Issued
Array ( [id] => 17478316 [patent_doc_number] => 20220085820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => FREQUENCY LOCKED LOOPS AND RELATED CIRCUITS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/377267 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377267 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377267
Frequency locked loops and related circuits and methods Jul 14, 2021 Issued
Array ( [id] => 18220071 [patent_doc_number] => 11595028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Frequency doubler with duty cycle correction [patent_app_type] => utility [patent_app_number] => 17/362509 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17791 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362509
Frequency doubler with duty cycle correction Jun 28, 2021 Issued
Array ( [id] => 17319979 [patent_doc_number] => 20210409029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Calibration of Sampling-Based Multiplying Delay-Locked Loop (MDLL) [patent_app_type] => utility [patent_app_number] => 17/357478 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357478
Calibration of sampling-based multiplying delay-locked loop (MDLL) Jun 23, 2021 Issued
Array ( [id] => 17303894 [patent_doc_number] => 20210399733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => DUAL MODE PHASE-LOCKED LOOP CIRCUIT, OSCILLATOR CIRCUIT, AND CONTROL METHOD OF OSCILLATOR CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/355180 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355180
Dual mode phase-locked loop circuit, oscillator circuit, and control method of oscillator circuit Jun 22, 2021 Issued
Array ( [id] => 18236559 [patent_doc_number] => 11601130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Initialization circuit of delay locked loop [patent_app_type] => utility [patent_app_number] => 17/304628 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304628
Initialization circuit of delay locked loop Jun 22, 2021 Issued
Array ( [id] => 18081848 [patent_doc_number] => 20220407460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => CURRENT MODE SIGNAL PATH OF AN INTEGRATED RADIO FREQUENCY PULSE GENERATOR [patent_app_type] => utility [patent_app_number] => 17/354718 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/354718
Current mode signal path of an integrated radio frequency pulse generator Jun 21, 2021 Issued
Array ( [id] => 19605665 [patent_doc_number] => 20240396545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => DRIVE CIRCUIT, ARRAY CIRCUIT, AND NEUROMORPHIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/572341 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18572341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/572341
DRIVE CIRCUIT, ARRAY CIRCUIT, AND NEUROMORPHIC DEVICE Jun 20, 2021 Pending
Array ( [id] => 17340132 [patent_doc_number] => 20220006463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => PHASE LOCKED LOOP CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/351300 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351300
Phase locked loop circuit Jun 17, 2021 Issued
Array ( [id] => 17530576 [patent_doc_number] => 11303285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Multi-mode design and operation for transistor mismatch immunity [patent_app_type] => utility [patent_app_number] => 17/340239 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8968 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 550 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340239
Multi-mode design and operation for transistor mismatch immunity Jun 6, 2021 Issued
Array ( [id] => 17901778 [patent_doc_number] => 20220311440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SINGLE LIVE LINE SWITCH CIRCUIT AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/334854 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334854
Single live line switch circuit and control method thereof May 30, 2021 Issued
Array ( [id] => 17824190 [patent_doc_number] => 11429138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Clock signal generating circuit [patent_app_type] => utility [patent_app_number] => 17/333889 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7412 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333889
Clock signal generating circuit May 27, 2021 Issued
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