Search

Didarul A. Mazumder

Examiner (ID: 7776, Phone: (571)272-8823 , Office: P/2819 )

Most Active Art Unit
2819
Art Unit(s)
2818, 2819, 2812
Total Applications
1039
Issued Applications
847
Pending Applications
115
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19546573 [patent_doc_number] => 20240363609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => METHOD OF FABRICATING PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/767970 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767970
METHOD OF FABRICATING PACKAGE STRUCTURE Jul 8, 2024 Pending
Array ( [id] => 19515726 [patent_doc_number] => 20240347412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => HEAT DISPERSION LAYERS FOR DOUBLE SIDED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/754753 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754753
HEAT DISPERSION LAYERS FOR DOUBLE SIDED INTERCONNECT Jun 25, 2024 Pending
Array ( [id] => 20404449 [patent_doc_number] => 12494430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Integrated circuit devices including lower interconnect metal layers at cell boundaries and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/752851 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 4555 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752851
Integrated circuit devices including lower interconnect metal layers at cell boundaries and methods of forming the same Jun 24, 2024 Issued
Array ( [id] => 19662225 [patent_doc_number] => 20240429290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => NEXFET NGEN3.2 MV DUAL SHIELD OXIDE DAMAGE SOLUTION [patent_app_type] => utility [patent_app_number] => 18/751877 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751877
NEXFET NGEN3.2 MV DUAL SHIELD OXIDE DAMAGE SOLUTION Jun 23, 2024 Pending
Array ( [id] => 20340247 [patent_doc_number] => 20250344367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DOUBLE SIDE WORD LINE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/739600 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739600
SEMICONDUCTOR DEVICE INCLUDING DOUBLE SIDE WORD LINE AND METHOD OF MANUFACTURING THE SAME Jun 10, 2024 Pending
Array ( [id] => 19468116 [patent_doc_number] => 20240321786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/735151 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735151
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Jun 4, 2024 Pending
Array ( [id] => 19452668 [patent_doc_number] => 20240312798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DIE PACKAGE WITH RING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/675560 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675560
Semiconductor die package with ring structure May 27, 2024 Issued
Array ( [id] => 19621491 [patent_doc_number] => 20240407171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/672106 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672106
SEMICONDUCTOR DEVICE May 22, 2024 Pending
Array ( [id] => 20369423 [patent_doc_number] => 20250359235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/672140 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672140
SEMICONDUCTOR DEVICE May 22, 2024 Pending
Array ( [id] => 19452798 [patent_doc_number] => 20240312928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/673099 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673099
Method of forming a region shielding within a package of a microelectronic device May 22, 2024 Issued
Array ( [id] => 19468152 [patent_doc_number] => 20240321822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR ASSEMBLIES WITH REDISTRIBUTION STRUCTURES FOR DIE STACK SIGNAL ROUTING [patent_app_type] => utility [patent_app_number] => 18/668777 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668777
Semiconductor assemblies with redistribution structures for die stack signal routing May 19, 2024 Issued
Array ( [id] => 19591810 [patent_doc_number] => 20240389367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => MANUFACTURING METHOD OF ORGANIC TRANSISTOR, ORGANIC TRANSISTOR, AND LIQUID CRYSTAL ELEMENT [patent_app_type] => utility [patent_app_number] => 18/666943 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666943 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666943
MANUFACTURING METHOD OF ORGANIC TRANSISTOR, ORGANIC TRANSISTOR, AND LIQUID CRYSTAL ELEMENT May 16, 2024 Pending
Array ( [id] => 20369430 [patent_doc_number] => 20250359242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => SEMICONDUCTOR DEVICE WITH BACKSIDE VIA [patent_app_type] => utility [patent_app_number] => 18/666769 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666769
SEMICONDUCTOR DEVICE WITH BACKSIDE VIA May 15, 2024 Pending
Array ( [id] => 19733927 [patent_doc_number] => 12211929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-28 [patent_title] => Heterojunction bipolar transistors with terminals having a non-planar arrangement [patent_app_type] => utility [patent_app_number] => 18/663523 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663523
Heterojunction bipolar transistors with terminals having a non-planar arrangement May 13, 2024 Issued
Array ( [id] => 19918576 [patent_doc_number] => 12293952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Electronic package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/659692 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 1057 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659692
Electronic package and manufacturing method thereof May 8, 2024 Issued
Array ( [id] => 19790278 [patent_doc_number] => 20250063957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/657229 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657229
VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME May 6, 2024 Pending
Array ( [id] => 19421016 [patent_doc_number] => 20240297140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => INTEGRATED CIRCUIT PACKAGES HAVING ADHESION LAYERS FOR THROUGH VIAS [patent_app_type] => utility [patent_app_number] => 18/656277 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656277
Integrated circuit packages having adhesion layers for through vias May 5, 2024 Issued
Array ( [id] => 19407163 [patent_doc_number] => 20240290674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/655822 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655822
Electronic package comprising conductive layer connected electrode pad through electronic component May 5, 2024 Issued
Array ( [id] => 20340246 [patent_doc_number] => 20250344366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DOUBLE SIDE WORD LINE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/653129 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653129 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653129
SEMICONDUCTOR DEVICE INCLUDING DOUBLE SIDE WORD LINE AND METHOD OF MANUFACTURING THE SAME May 1, 2024 Pending
Array ( [id] => 20637988 [patent_doc_number] => 12598887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Display panel having an arrangement by unit pixel pairs [patent_app_type] => utility [patent_app_number] => 18/646520 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646520
Display panel having an arrangement by unit pixel pairs Apr 24, 2024 Issued
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