
Didarul A. Mazumder
Examiner (ID: 7776, Phone: (571)272-8823 , Office: P/2819 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2818, 2819, 2812 |
| Total Applications | 1039 |
| Issued Applications | 847 |
| Pending Applications | 115 |
| Abandoned Applications | 103 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20553269
[patent_doc_number] => 12564084
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-24
[patent_title] => Bonded structures without intervening adhesive
[patent_app_type] => utility
[patent_app_number] => 18/462691
[patent_app_country] => US
[patent_app_date] => 2023-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 48
[patent_no_of_words] => 1862
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462691
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/462691 | Bonded structures without intervening adhesive | Sep 6, 2023 | Issued |
Array
(
[id] => 19821143
[patent_doc_number] => 20250079350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => Semiconductor Device and Method of Forming AIP Structure to Reduce Signal Interference Among and Between Encapsulant Blocks
[patent_app_type] => utility
[patent_app_number] => 18/462204
[patent_app_country] => US
[patent_app_date] => 2023-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4554
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 15
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462204
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/462204 | Semiconductor Device and Method of Forming AIP Structure to Reduce Signal Interference Among and Between Encapsulant Blocks | Sep 5, 2023 | Pending |
Array
(
[id] => 20748504
[patent_doc_number] => 12648447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Chip package with electromagnetic interference (EMI) shielding layer and ground wire and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/242506
[patent_app_country] => US
[patent_app_date] => 2023-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 0
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242506
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/242506 | Chip package with electromagnetic interference (EMI) shielding layer and ground wire and method of manufacturing the same | Sep 4, 2023 | Issued |
Array
(
[id] => 19116652
[patent_doc_number] => 20240128402
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE ARRAY INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/241589
[patent_app_country] => US
[patent_app_date] => 2023-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10546
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18241589
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/241589 | LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE ARRAY INCLUDING THE SAME | Aug 31, 2023 | Pending |
Array
(
[id] => 19116425
[patent_doc_number] => 20240128175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/459821
[patent_app_country] => US
[patent_app_date] => 2023-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7709
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459821
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/459821 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | Aug 31, 2023 | Pending |
Array
(
[id] => 20827689
[patent_doc_number] => 12681249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-14
[patent_title] => 3D system and wafer reconstitution with mid-layer interposer
[patent_app_type] => utility
[patent_app_number] => 18/458892
[patent_app_country] => US
[patent_app_date] => 2023-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 45
[patent_no_of_words] => 4332
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458892
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458892 | 3D system and wafer reconstitution with mid-layer interposer | Aug 29, 2023 | Issued |
Array
(
[id] => 20705953
[patent_doc_number] => 12628685
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-12
[patent_title] => Double-sided multichip packages with direct die-to-die coupling
[patent_app_type] => utility
[patent_app_number] => 18/458705
[patent_app_country] => US
[patent_app_date] => 2023-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3223
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 306
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458705
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458705 | Double-sided multichip packages with direct die-to-die coupling | Aug 29, 2023 | Issued |
Array
(
[id] => 18851223
[patent_doc_number] => 20230413627
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/458218
[patent_app_country] => US
[patent_app_date] => 2023-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9618
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458218
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458218 | Display device comprising sealing film including stacked insulating layers | Aug 29, 2023 | Issued |
Array
(
[id] => 19634648
[patent_doc_number] => 20240413097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => STRESS BUFFER IN INTEGRATED CIRCUIT PACKAGE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/451269
[patent_app_country] => US
[patent_app_date] => 2023-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8855
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451269
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/451269 | STRESS BUFFER IN INTEGRATED CIRCUIT PACKAGE AND METHOD | Aug 16, 2023 | Pending |
Array
(
[id] => 19255308
[patent_doc_number] => 20240206305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/450587
[patent_app_country] => US
[patent_app_date] => 2023-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450587
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/450587 | DISPLAY DEVICE | Aug 15, 2023 | Pending |
Array
(
[id] => 18812995
[patent_doc_number] => 20230387332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => SCATTERING STRUCTURES FOR SINGLE-PHOTON AVALANCHE DIODES
[patent_app_type] => utility
[patent_app_number] => 18/449356
[patent_app_country] => US
[patent_app_date] => 2023-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5729
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449356
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/449356 | Scattering structures for single-photon avalanche diodes | Aug 13, 2023 | Issued |
Array
(
[id] => 19087899
[patent_doc_number] => 20240114700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/448615
[patent_app_country] => US
[patent_app_date] => 2023-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12352
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448615
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/448615 | Semiconductor device having improved device bonding features, performance and reliability | Aug 10, 2023 | Issued |
Array
(
[id] => 20118359
[patent_doc_number] => 12368077
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Semiconductor package and method comprising formation of redistribution structure and interconnecting die
[patent_app_type] => utility
[patent_app_number] => 18/446748
[patent_app_country] => US
[patent_app_date] => 2023-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 30
[patent_no_of_words] => 5559
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446748
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/446748 | Semiconductor package and method comprising formation of redistribution structure and interconnecting die | Aug 8, 2023 | Issued |
Array
(
[id] => 18832172
[patent_doc_number] => 20230400699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => MULTIFUNCTIONAL COLLIMATOR FOR CONTACT IMAGE SENSORS
[patent_app_type] => utility
[patent_app_number] => 18/231760
[patent_app_country] => US
[patent_app_date] => 2023-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6084
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231760
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/231760 | Multifunctional collimator for contact image sensors | Aug 7, 2023 | Issued |
Array
(
[id] => 19672754
[patent_doc_number] => 12185550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-31
[patent_title] => Through array contact structure of three-dimensional memory device
[patent_app_type] => utility
[patent_app_number] => 18/231749
[patent_app_country] => US
[patent_app_date] => 2023-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 12800
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231749
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/231749 | Through array contact structure of three-dimensional memory device | Aug 7, 2023 | Issued |
Array
(
[id] => 18975275
[patent_doc_number] => 20240055367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => METHOD FOR FORMING A PARTIAL SHIELDING FOR AN ELECTRONIC ASSEMBLY
[patent_app_type] => utility
[patent_app_number] => 18/363773
[patent_app_country] => US
[patent_app_date] => 2023-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5011
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363773
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/363773 | Method for forming a partial shielding for an electronic assembly | Aug 1, 2023 | Issued |
Array
(
[id] => 19261076
[patent_doc_number] => 12021143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-25
[patent_title] => P-type strained channel in a fin field effect transistor (FinFET) device
[patent_app_type] => utility
[patent_app_number] => 18/362210
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 26
[patent_no_of_words] => 9603
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362210
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362210 | P-type strained channel in a fin field effect transistor (FinFET) device | Jul 30, 2023 | Issued |
Array
(
[id] => 19023204
[patent_doc_number] => 20240079375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-07
[patent_title] => BONDING TOOL, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/359020
[patent_app_country] => US
[patent_app_date] => 2023-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10141
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359020
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/359020 | BONDING TOOL, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE | Jul 25, 2023 | Pending |
Array
(
[id] => 18774461
[patent_doc_number] => 20230369292
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => CHIP STACKING STRUCTURE AND PREPARATION METHOD THEREOF, CHIP STACKING PACKAGE, AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/358102
[patent_app_country] => US
[patent_app_date] => 2023-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8752
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358102
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/358102 | Chip stacking structure and preparation method thereof, chip stacking package, and electronic device | Jul 24, 2023 | Issued |
Array
(
[id] => 20748506
[patent_doc_number] => 12648449
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Integrated circuit (IC) package including an inductive device formed in a conductive routing region
[patent_app_type] => utility
[patent_app_number] => 18/351591
[patent_app_country] => US
[patent_app_date] => 2023-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 3100
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351591
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/351591 | Integrated circuit (IC) package including an inductive device formed in a conductive routing region | Jul 12, 2023 | Issued |