
Dilinh P. Nguyen
Examiner (ID: 17194, Phone: (571)272-1712 , Office: P/2893 )
| Most Active Art Unit | 2893 |
| Art Unit(s) | 2894, 2818, 2893, 2814 |
| Total Applications | 984 |
| Issued Applications | 760 |
| Pending Applications | 22 |
| Abandoned Applications | 204 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17758122
[patent_doc_number] => 11398421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => Semiconductor substrate and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/247441
[patent_app_country] => US
[patent_app_date] => 2019-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 52
[patent_no_of_words] => 10007
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247441
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/247441 | Semiconductor substrate and method for manufacturing the same | Jan 13, 2019 | Issued |
Array
(
[id] => 16119833
[patent_doc_number] => 20200211939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => PACKAGED ELECTRONIC DEVICE WITH SUSPENDED MAGNETIC SUBASSEMBLY
[patent_app_type] => utility
[patent_app_number] => 16/236730
[patent_app_country] => US
[patent_app_date] => 2018-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236730
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/236730 | Packaged electronic device with suspended magnetic subassembly | Dec 30, 2018 | Issued |
Array
(
[id] => 14285219
[patent_doc_number] => 20190139894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => BICONVEX LOW RESISTANCE METAL WIRE
[patent_app_type] => utility
[patent_app_number] => 16/235540
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6381
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235540
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/235540 | Biconvex low resistance metal wire | Dec 27, 2018 | Issued |
Array
(
[id] => 15274373
[patent_doc_number] => 20190385921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => PACKAGING STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/235389
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5618
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235389
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/235389 | Packaging structure | Dec 27, 2018 | Issued |
Array
(
[id] => 15598069
[patent_doc_number] => 20200075569
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/233653
[patent_app_country] => US
[patent_app_date] => 2018-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9647
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233653
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/233653 | Multi fan-out package structure and method for forming the same | Dec 26, 2018 | Issued |
Array
(
[id] => 16638307
[patent_doc_number] => 10916829
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Semiconductor package structure having antenna module
[patent_app_type] => utility
[patent_app_number] => 16/233021
[patent_app_country] => US
[patent_app_date] => 2018-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4728
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233021
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/233021 | Semiconductor package structure having antenna module | Dec 25, 2018 | Issued |
Array
(
[id] => 17122421
[patent_doc_number] => 11133568
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-28
[patent_title] => Semiconductor package structure having antenna module
[patent_app_type] => utility
[patent_app_number] => 16/233040
[patent_app_country] => US
[patent_app_date] => 2018-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4512
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233040
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/233040 | Semiconductor package structure having antenna module | Dec 25, 2018 | Issued |
Array
(
[id] => 15717747
[patent_doc_number] => 20200105641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => PACKAGE STRUCTURES AND METHODS OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/231964
[patent_app_country] => US
[patent_app_date] => 2018-12-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231964
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/231964 | Package structures | Dec 24, 2018 | Issued |
Array
(
[id] => 16098567
[patent_doc_number] => 20200203270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => SEMICONDCUTOR PACKAGE AND METHOD OF DICING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/231614
[patent_app_country] => US
[patent_app_date] => 2018-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5077
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231614
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/231614 | Semiconductor package with chamfered semiconductor device | Dec 23, 2018 | Issued |
Array
(
[id] => 16098629
[patent_doc_number] => 20200203301
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => ELECTRONIC ASSEMBLY, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/231619
[patent_app_country] => US
[patent_app_date] => 2018-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5643
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231619
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/231619 | Electronic assembly, package structure having hollow cylinders and method of fabricating the same | Dec 23, 2018 | Issued |
Array
(
[id] => 16098587
[patent_doc_number] => 20200203280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/231622
[patent_app_country] => US
[patent_app_date] => 2018-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6718
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231622
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/231622 | Semiconductor package structure comprising rigid-flexible substrate and manufacturing method thereof | Dec 23, 2018 | Issued |
Array
(
[id] => 14191125
[patent_doc_number] => 20190115268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-18
[patent_title] => Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in FO-WLCSP
[patent_app_type] => utility
[patent_app_number] => 16/218823
[patent_app_country] => US
[patent_app_date] => 2018-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6190
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218823
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/218823 | Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP | Dec 12, 2018 | Issued |
Array
(
[id] => 17941711
[patent_doc_number] => 11476170
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-18
[patent_title] => Power semiconductor module and power conversion apparatus
[patent_app_type] => utility
[patent_app_number] => 17/046303
[patent_app_country] => US
[patent_app_date] => 2018-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 12474
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17046303
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/046303 | Power semiconductor module and power conversion apparatus | Dec 5, 2018 | Issued |
Array
(
[id] => 16000953
[patent_doc_number] => 20200176347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => THERMALLY ENHANCED PACKAGE AND PROCESS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/204214
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204214 | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same | Nov 28, 2018 | Issued |
Array
(
[id] => 16000953
[patent_doc_number] => 20200176347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => THERMALLY ENHANCED PACKAGE AND PROCESS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/204214
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204214 | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same | Nov 28, 2018 | Issued |
Array
(
[id] => 16000953
[patent_doc_number] => 20200176347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => THERMALLY ENHANCED PACKAGE AND PROCESS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/204214
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204214 | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same | Nov 28, 2018 | Issued |
Array
(
[id] => 16000953
[patent_doc_number] => 20200176347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => THERMALLY ENHANCED PACKAGE AND PROCESS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/204214
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204214 | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same | Nov 28, 2018 | Issued |
Array
(
[id] => 16000953
[patent_doc_number] => 20200176347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => THERMALLY ENHANCED PACKAGE AND PROCESS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/204214
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204214 | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same | Nov 28, 2018 | Issued |
Array
(
[id] => 16000953
[patent_doc_number] => 20200176347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => THERMALLY ENHANCED PACKAGE AND PROCESS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/204214
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204214 | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same | Nov 28, 2018 | Issued |
Array
(
[id] => 16000953
[patent_doc_number] => 20200176347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => THERMALLY ENHANCED PACKAGE AND PROCESS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/204214
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204214 | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same | Nov 28, 2018 | Issued |