
Dimary S. Lopez Cruz
Examiner (ID: 12613, Phone: (571)270-7893 , Office: P/2848 )
| Most Active Art Unit | 2848 |
| Art Unit(s) | 2848, 2845, 2835 |
| Total Applications | 546 |
| Issued Applications | 403 |
| Pending Applications | 13 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4965043
[patent_doc_number] => 20080107863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'MULTILAYERED PRINTED WIRING BOARD'
[patent_app_type] => utility
[patent_app_number] => 11/935207
[patent_app_country] => US
[patent_app_date] => 2007-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9118
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0107/20080107863.pdf
[firstpage_image] =>[orig_patent_app_number] => 11935207
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/935207 | Multilayered printed wiring board with a multilayered core substrate | Nov 4, 2007 | Issued |
Array
(
[id] => 5327228
[patent_doc_number] => 20090107705
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'METHODS AND SYSTEMS FOR REDUCING NOISE COUPLING IN HIGH SPEED DIGITAL SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 11/924416
[patent_app_country] => US
[patent_app_date] => 2007-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2281
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0107/20090107705.pdf
[firstpage_image] =>[orig_patent_app_number] => 11924416
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/924416 | Reducing noise coupling in high speed digital systems | Oct 24, 2007 | Issued |
Array
(
[id] => 8115351
[patent_doc_number] => 08158892
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-17
[patent_title] => 'High-speed router with backplane using muli-diameter drilled thru-holes and vias'
[patent_app_type] => utility
[patent_app_number] => 11/891785
[patent_app_country] => US
[patent_app_date] => 2007-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 6545
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/158/08158892.pdf
[firstpage_image] =>[orig_patent_app_number] => 11891785
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/891785 | High-speed router with backplane using muli-diameter drilled thru-holes and vias | Aug 12, 2007 | Issued |
Array
(
[id] => 8270647
[patent_doc_number] => 08212145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-03
[patent_title] => 'Circuit unit accommodation box'
[patent_app_type] => utility
[patent_app_number] => 12/442342
[patent_app_country] => US
[patent_app_date] => 2007-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 38
[patent_no_of_words] => 9084
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12442342
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/442342 | Circuit unit accommodation box | Aug 7, 2007 | Issued |
Array
(
[id] => 6495457
[patent_doc_number] => 20100012358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-21
[patent_title] => 'CIRCUIT CONNECTING MATERIAL, CONNECTION STRUCTURE FOR CIRCUIT MEMBER USING THE SAME AND PRODUCTION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/438883
[patent_app_country] => US
[patent_app_date] => 2007-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12704
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20100012358.pdf
[firstpage_image] =>[orig_patent_app_number] => 12438883
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/438883 | CIRCUIT CONNECTING MATERIAL, CONNECTION STRUCTURE FOR CIRCUIT MEMBER USING THE SAME AND PRODUCTION METHOD THEREOF | Aug 5, 2007 | Abandoned |
Array
(
[id] => 6526561
[patent_doc_number] => 20100270070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-28
[patent_title] => 'ISOLATION'
[patent_app_type] => utility
[patent_app_number] => 12/295140
[patent_app_country] => US
[patent_app_date] => 2007-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4239
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20100270070.pdf
[firstpage_image] =>[orig_patent_app_number] => 12295140
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/295140 | ISOLATION | Mar 27, 2007 | Abandoned |
Array
(
[id] => 8944251
[patent_doc_number] => 08497431
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-30
[patent_title] => 'Circuit connection material, circuit member connecting structure and method of connecting circuit member'
[patent_app_type] => utility
[patent_app_number] => 12/374628
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7620
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12374628
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/374628 | Circuit connection material, circuit member connecting structure and method of connecting circuit member | Jul 20, 2006 | Issued |
Array
(
[id] => 6536648
[patent_doc_number] => 20100044088
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-25
[patent_title] => 'CONDUCTIVE ADHESIVE'
[patent_app_type] => utility
[patent_app_number] => 12/307318
[patent_app_country] => US
[patent_app_date] => 2006-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4454
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20100044088.pdf
[firstpage_image] =>[orig_patent_app_number] => 12307318
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/307318 | CONDUCTIVE ADHESIVE | Jul 4, 2006 | Abandoned |
Array
(
[id] => 5584072
[patent_doc_number] => 20090103274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'WARPAGE PREVENTING SUBSTRATES AND METHOD OF MAKING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/917613
[patent_app_country] => US
[patent_app_date] => 2006-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2889
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0103/20090103274.pdf
[firstpage_image] =>[orig_patent_app_number] => 11917613
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/917613 | Warpage preventing substrates | Jun 22, 2006 | Issued |
Array
(
[id] => 6214717
[patent_doc_number] => 20100051324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'DIELECTRIC SUBSTRATE WITH HOLES AND METHOD OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 11/917445
[patent_app_country] => US
[patent_app_date] => 2006-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5452
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20100051324.pdf
[firstpage_image] =>[orig_patent_app_number] => 11917445
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/917445 | DIELECTRIC SUBSTRATE WITH HOLES AND METHOD OF MANUFACTURE | Jun 19, 2006 | Abandoned |
Array
(
[id] => 5327230
[patent_doc_number] => 20090107707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'Conductive Paste and Wiring Board Using It'
[patent_app_type] => utility
[patent_app_number] => 11/887835
[patent_app_country] => US
[patent_app_date] => 2006-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 6758
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0107/20090107707.pdf
[firstpage_image] =>[orig_patent_app_number] => 11887835
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/887835 | Conductive paste and wiring board using it | May 21, 2006 | Issued |
Array
(
[id] => 7978269
[patent_doc_number] => 08071882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Metal base circuit board, LED, and LED light source unit'
[patent_app_type] => utility
[patent_app_number] => 11/911914
[patent_app_country] => US
[patent_app_date] => 2006-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 26923
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/071/08071882.pdf
[firstpage_image] =>[orig_patent_app_number] => 11911914
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/911914 | Metal base circuit board, LED, and LED light source unit | Apr 18, 2006 | Issued |
Array
(
[id] => 5299506
[patent_doc_number] => 20090294158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-03
[patent_title] => 'ELECTRONIC CIRCUIT AND METHOD FOR MANUFACTURING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/814847
[patent_app_country] => US
[patent_app_date] => 2006-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4252
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0294/20090294158.pdf
[firstpage_image] =>[orig_patent_app_number] => 11814847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/814847 | ELECTRONIC CIRCUIT AND METHOD FOR MANUFACTURING SAME | Mar 8, 2006 | Abandoned |
Array
(
[id] => 6584141
[patent_doc_number] => 20100000772
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-07
[patent_title] => 'ELECTRONIC PACKAGE HAVING DOWN-SET LEADS AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/575204
[patent_app_country] => US
[patent_app_date] => 2004-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3755
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20100000772.pdf
[firstpage_image] =>[orig_patent_app_number] => 11575204
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/575204 | Electronic package having down-set leads and method | Dec 19, 2004 | Issued |