Search

Dinh X. Nguyen

Examiner (ID: 14225)

Most Active Art Unit
3738
Art Unit(s)
3738, 3626
Total Applications
343
Issued Applications
250
Pending Applications
67
Abandoned Applications
26

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12262620 [patent_doc_number] => 20180081816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'MEMORY MANAGEMENT SUPPORTING HUGE PAGES' [patent_app_type] => utility [patent_app_number] => 15/273433 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273433 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273433
Memory management supporting huge pages Sep 21, 2016 Issued
Array ( [id] => 16610040 [patent_doc_number] => 10911065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Computer system and method including selectively compressing data files and directories based on an operator indication and representing the amount of available free space [patent_app_type] => utility [patent_app_number] => 15/270182 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9733 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270182 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270182
Computer system and method including selectively compressing data files and directories based on an operator indication and representing the amount of available free space Sep 19, 2016 Issued
Array ( [id] => 14766115 [patent_doc_number] => 10394453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Method and system for choosing an optimal compression algorithm considering resources [patent_app_type] => utility [patent_app_number] => 15/267790 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/267790
Method and system for choosing an optimal compression algorithm considering resources Sep 15, 2016 Issued
Array ( [id] => 13003671 [patent_doc_number] => 10025503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Autonomous dynamic optimization of platform resources [patent_app_type] => utility [patent_app_number] => 15/243590 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5608 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15243590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/243590
Autonomous dynamic optimization of platform resources Aug 21, 2016 Issued
Array ( [id] => 11292427 [patent_doc_number] => 20160342359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'METHOD FOR SELECTIVELY PERFORMING A SECURE DATA ERASE TO ENSURE TIMELY ERASURE' [patent_app_type] => utility [patent_app_number] => 15/225653 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8333 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225653 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225653
Method for selectively performing a secure data erase to ensure timely erasure Jul 31, 2016 Issued
Array ( [id] => 13055315 [patent_doc_number] => 10049050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Locking a cache line for write operations on a bus [patent_app_type] => utility [patent_app_number] => 15/219068 [patent_app_country] => US [patent_app_date] => 2016-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4389 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219068 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219068
Locking a cache line for write operations on a bus Jul 24, 2016 Issued
Array ( [id] => 13268721 [patent_doc_number] => 10146445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Mechanism for enabling full data bus utilization without increasing data granularity [patent_app_type] => utility [patent_app_number] => 15/209429 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/209429
Mechanism for enabling full data bus utilization without increasing data granularity Jul 12, 2016 Issued
Array ( [id] => 13055003 [patent_doc_number] => 10048890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => Synchronizing catalogs of virtual machine copies [patent_app_type] => utility [patent_app_number] => 15/200222 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15200222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/200222
Synchronizing catalogs of virtual machine copies Jun 30, 2016 Issued
Array ( [id] => 11403609 [patent_doc_number] => 20170024147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'STORAGE CONTROL DEVICE AND HIERARCHIZED STORAGE CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 15/200010 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8817 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15200010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/200010
STORAGE CONTROL DEVICE AND HIERARCHIZED STORAGE CONTROL METHOD Jun 30, 2016 Abandoned
Array ( [id] => 11116950 [patent_doc_number] => 20160313924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'TRACKING OWNERSHIP OF MEMORY IN A DATA PROCESSING SYSTEM THROUGH USE OF A MEMORY MONITOR' [patent_app_type] => utility [patent_app_number] => 15/200986 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3688 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15200986 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/200986
Tracking ownership of memory in a data processing system through use of a memory monitor Jun 30, 2016 Issued
Array ( [id] => 13919505 [patent_doc_number] => 10203875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-12 [patent_title] => Methods and systems for implementing high bandwidth memory command address bus training [patent_app_type] => utility [patent_app_number] => 15/199921 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6720 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199921
Methods and systems for implementing high bandwidth memory command address bus training Jun 29, 2016 Issued
Array ( [id] => 12550905 [patent_doc_number] => 10013184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => Pipelined counter signatures [patent_app_type] => utility [patent_app_number] => 15/199929 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199929 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199929
Pipelined counter signatures Jun 29, 2016 Issued
Array ( [id] => 14600793 [patent_doc_number] => 10353588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-16 [patent_title] => Managing dynamic resource reservation for host I/O requests [patent_app_type] => utility [patent_app_number] => 15/199975 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6509 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199975 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199975
Managing dynamic resource reservation for host I/O requests Jun 29, 2016 Issued
Array ( [id] => 16478010 [patent_doc_number] => 10852956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering [patent_app_type] => utility [patent_app_number] => 15/199951 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199951
Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering Jun 29, 2016 Issued
Array ( [id] => 13003685 [patent_doc_number] => 10025510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-17 [patent_title] => Technique for copying unallocated logical regions of thin logical units [patent_app_type] => utility [patent_app_number] => 15/199972 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6877 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199972
Technique for copying unallocated logical regions of thin logical units Jun 29, 2016 Issued
Array ( [id] => 13975141 [patent_doc_number] => 10216927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => System and method for protecting memory pages associated with a process using a virtualization layer [patent_app_type] => utility [patent_app_number] => 15/199879 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 13022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199879
System and method for protecting memory pages associated with a process using a virtualization layer Jun 29, 2016 Issued
Array ( [id] => 13893065 [patent_doc_number] => 10199084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Techniques to use chip select signals for a dual in-line memory module [patent_app_type] => utility [patent_app_number] => 15/197424 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11504 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197424 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/197424
Techniques to use chip select signals for a dual in-line memory module Jun 28, 2016 Issued
Array ( [id] => 15248155 [patent_doc_number] => 10509602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Data storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/195462 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7911 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/195462
Data storage device and operating method thereof Jun 27, 2016 Issued
Array ( [id] => 13568975 [patent_doc_number] => 20180336035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => METHOD AND APPARATUS FOR PROCESSING INSTRUCTIONS USING PROCESSING-IN-MEMORY [patent_app_type] => utility [patent_app_number] => 15/768254 [patent_app_country] => US [patent_app_date] => 2016-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15768254 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/768254
Method and apparatus for processing instructions using processing-in-memory Jun 9, 2016 Issued
Array ( [id] => 11530999 [patent_doc_number] => 20170090977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'DYNAMIC RELEASING OF CACHE LINES' [patent_app_type] => utility [patent_app_number] => 15/165308 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 17833 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165308
Dynamic releasing of cache lines May 25, 2016 Issued
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