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Dinku W. Gebresenbet

Examiner (ID: 6582, Phone: (571)270-1636 , Office: P/2164 )

Most Active Art Unit
2164
Art Unit(s)
2164
Total Applications
651
Issued Applications
441
Pending Applications
41
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15093159 [patent_doc_number] => 20190341391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/511111 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511111
Semiconductor memory device and method for manufacturing the same Jul 14, 2019 Issued
Array ( [id] => 17048300 [patent_doc_number] => 11101491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Semiconductor structures having a micro-battery and methods for making the same [patent_app_type] => utility [patent_app_number] => 16/449522 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16449522 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/449522
Semiconductor structures having a micro-battery and methods for making the same Jun 23, 2019 Issued
Array ( [id] => 16202070 [patent_doc_number] => 10727250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Methods used in forming an array of elevationally-extending transistors [patent_app_type] => utility [patent_app_number] => 16/430713 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6265 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430713
Methods used in forming an array of elevationally-extending transistors Jun 3, 2019 Issued
Array ( [id] => 19155172 [patent_doc_number] => 11980109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Selection element-integrated phase-change memory and method for producing same [patent_app_type] => utility [patent_app_number] => 17/051268 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6778 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17051268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/051268
Selection element-integrated phase-change memory and method for producing same May 22, 2019 Issued
Array ( [id] => 18001141 [patent_doc_number] => 11502253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Phase transformation electronic device [patent_app_type] => utility [patent_app_number] => 16/420155 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 8133 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420155
Phase transformation electronic device May 21, 2019 Issued
Array ( [id] => 14813063 [patent_doc_number] => 20190273141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 16/418617 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/418617
Semiconductor device and semiconductor module May 20, 2019 Issued
Array ( [id] => 14753231 [patent_doc_number] => 20190259789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SEMICONDUCTOR STRUCTURE, BACK-SIDE ILLUMINATED IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/404436 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404436 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404436
Semiconductor structure, back-side illuminated image sensor and method for manufacturing the same May 5, 2019 Issued
Array ( [id] => 15139749 [patent_doc_number] => 10483362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => High electron mobility transistor devices and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/394701 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3658 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16394701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/394701
High electron mobility transistor devices and method for fabricating the same Apr 24, 2019 Issued
Array ( [id] => 16081459 [patent_doc_number] => 20200194716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/603243 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603243
Display device Apr 24, 2019 Issued
Array ( [id] => 15760643 [patent_doc_number] => 10622453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Vertical MOS transistor [patent_app_type] => utility [patent_app_number] => 16/390210 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 28 [patent_no_of_words] => 4528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390210
Vertical MOS transistor Apr 21, 2019 Issued
Array ( [id] => 15000461 [patent_doc_number] => 20190319188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => NANO MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/381641 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381641 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381641
Nano memory device Apr 10, 2019 Issued
Array ( [id] => 16172878 [patent_doc_number] => 10714456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Dual sided fan-out package having low warpage across all temperatures [patent_app_type] => utility [patent_app_number] => 16/379078 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 7401 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/379078
Dual sided fan-out package having low warpage across all temperatures Apr 8, 2019 Issued
Array ( [id] => 14676797 [patent_doc_number] => 20190237513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SOLID STATE IMAGE SENSOR, PRODUCTION METHOD THEREOF AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/378339 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378339
Solid state image sensor, production method thereof and electronic device Apr 7, 2019 Issued
Array ( [id] => 16845936 [patent_doc_number] => 11018032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => High pressure and high temperature anneal chamber [patent_app_type] => utility [patent_app_number] => 16/378140 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7202 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378140
High pressure and high temperature anneal chamber Apr 7, 2019 Issued
Array ( [id] => 16332657 [patent_doc_number] => 20200303623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => INTERCONNECT STRUCTURES FOR LOGIC AND MEMORY DEVICES AND METHODS OF FABRICATION [patent_app_type] => utility [patent_app_number] => 16/358671 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358671
Interconnect structures for logic and memory devices and methods of fabrication Mar 18, 2019 Issued
Array ( [id] => 15580931 [patent_doc_number] => 10580860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Integration methods to fabricate internal spacers for nanowire devices [patent_app_type] => utility [patent_app_number] => 16/358613 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7879 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358613
Integration methods to fabricate internal spacers for nanowire devices Mar 18, 2019 Issued
Array ( [id] => 17210877 [patent_doc_number] => 11171256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Process for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters [patent_app_type] => utility [patent_app_number] => 16/352029 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 8760 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352029 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352029
Process for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters Mar 12, 2019 Issued
Array ( [id] => 14573581 [patent_doc_number] => 20190214398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => STACKED FINFET EEPROM [patent_app_type] => utility [patent_app_number] => 16/352222 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352222
Stacked FinFET EEPROM Mar 12, 2019 Issued
Array ( [id] => 15564921 [patent_doc_number] => 20200066872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH INNER SPACER LAYER [patent_app_type] => utility [patent_app_number] => 16/299531 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299531
Method for forming semiconductor device structure with inner spacer layer Mar 11, 2019 Issued
Array ( [id] => 16448154 [patent_doc_number] => 10840085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Method for improving bonding of dangling bonds of silicon atoms [patent_app_type] => utility [patent_app_number] => 16/351407 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2484 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16351407 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/351407
Method for improving bonding of dangling bonds of silicon atoms Mar 11, 2019 Issued
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