Search

Dinku W. Gebresenbet

Examiner (ID: 6582, Phone: (571)270-1636 , Office: P/2164 )

Most Active Art Unit
2164
Art Unit(s)
2164
Total Applications
651
Issued Applications
441
Pending Applications
41
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14079959 [patent_doc_number] => 20190088867 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2019-03-21 [patent_title] => PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS [patent_app_type] => utility [patent_app_number] => 15/882666 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882666
Phase change memory stack with treated sidewalls Jan 28, 2018 Issued
Array ( [id] => 14920525 [patent_doc_number] => 10431590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/863490 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 36 [patent_no_of_words] => 6697 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863490
Semiconductor memory device and method for manufacturing the same Jan 4, 2018 Issued
Array ( [id] => 14011747 [patent_doc_number] => 10224349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-05 [patent_title] => Method of manufacturing TFT array substrate and display device [patent_app_type] => utility [patent_app_number] => 15/743292 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3274 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743292 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/743292
Method of manufacturing TFT array substrate and display device Jan 3, 2018 Issued
Array ( [id] => 16249469 [patent_doc_number] => 10748844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Stress isolation for silicon photonic applications [patent_app_type] => utility [patent_app_number] => 15/859331 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7790 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859331 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859331
Stress isolation for silicon photonic applications Dec 29, 2017 Issued
Array ( [id] => 14366819 [patent_doc_number] => 10304721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => Formation of isolation layers using a dry-wet-dry oxidation technique [patent_app_type] => utility [patent_app_number] => 15/859447 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3892 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859447
Formation of isolation layers using a dry-wet-dry oxidation technique Dec 29, 2017 Issued
Array ( [id] => 13951223 [patent_doc_number] => 10211395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-19 [patent_title] => Method for combining NVM class and SRAM class MRAM elements on the same chip [patent_app_type] => utility [patent_app_number] => 15/859451 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859451
Method for combining NVM class and SRAM class MRAM elements on the same chip Dec 29, 2017 Issued
Array ( [id] => 14542291 [patent_doc_number] => 20190206767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => DUAL-DAMASCENE ZERO-MISALIGNMENT-VIA PROCESS FOR SEMICONDUCTOR PACKAGING [patent_app_type] => utility [patent_app_number] => 15/859332 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859332
Dual-damascene zero-misalignment-via process for semiconductor packaging Dec 29, 2017 Issued
Array ( [id] => 14738897 [patent_doc_number] => 10388860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Method for manufacturing high density magnetic random access memory devices using diamond like carbon hard mask [patent_app_type] => utility [patent_app_number] => 15/859459 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5910 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859459
Method for manufacturing high density magnetic random access memory devices using diamond like carbon hard mask Dec 29, 2017 Issued
Array ( [id] => 14382097 [patent_doc_number] => 20190164961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => FIN END PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 15/859351 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859351 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859351
Fin end plug structures for advanced integrated circuit structure fabrication Dec 29, 2017 Issued
Array ( [id] => 15061363 [patent_doc_number] => 10460993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Fin cut and fin trim isolation for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 15/859327 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73698 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859327
Fin cut and fin trim isolation for advanced integrated circuit structure fabrication Dec 28, 2017 Issued
Array ( [id] => 16264756 [patent_doc_number] => 10756204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 15/859326 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73630 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859326 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859326
Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication Dec 28, 2017 Issued
Array ( [id] => 13214957 [patent_doc_number] => 10121856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Integration methods to fabricate internal spacers for nanowire devices [patent_app_type] => utility [patent_app_number] => 15/859226 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7823 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859226
Integration methods to fabricate internal spacers for nanowire devices Dec 28, 2017 Issued
Array ( [id] => 14644777 [patent_doc_number] => 10367139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Methods of manufacturing magnetic tunnel junction devices [patent_app_type] => utility [patent_app_number] => 15/859230 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 5111 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859230
Methods of manufacturing magnetic tunnel junction devices Dec 28, 2017 Issued
Array ( [id] => 12644553 [patent_doc_number] => 20180106682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => FABRICATION METHOD FOR MICROMECHANICAL SENSORS [patent_app_type] => utility [patent_app_number] => 15/836535 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836535
Fabrication method for micromechanical sensors Dec 7, 2017 Issued
Array ( [id] => 12615285 [patent_doc_number] => 20180096925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SINGLE OR MULTI CHIP MODULE PACKAGE AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 15/833533 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833533 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/833533
Single or multi chip module package and related methods Dec 5, 2017 Issued
Array ( [id] => 12791359 [patent_doc_number] => 20180155622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => LIGHTING DEVICES WITH PRESCRIBED COLOUR EMISSION [patent_app_type] => utility [patent_app_number] => 15/831953 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831953
LIGHTING DEVICES WITH PRESCRIBED COLOUR EMISSION Dec 4, 2017 Abandoned
Array ( [id] => 14381733 [patent_doc_number] => 20190164779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => CORROSION-RESISTANT SOLID-STATE PHOTO-ELECTRODE [patent_app_type] => utility [patent_app_number] => 15/825361 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825361 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825361
CORROSION-RESISTANT SOLID-STATE PHOTO-ELECTRODE Nov 28, 2017 Abandoned
Array ( [id] => 14955043 [patent_doc_number] => 10438800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Semiconductor devices and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/825135 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 10901 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825135
Semiconductor devices and methods of fabricating the same Nov 28, 2017 Issued
Array ( [id] => 13278949 [patent_doc_number] => 10151048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-11 [patent_title] => Manufacturing method of epitaxial contact structure in semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/825127 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825127
Manufacturing method of epitaxial contact structure in semiconductor memory device Nov 28, 2017 Issued
Array ( [id] => 14382135 [patent_doc_number] => 20190164980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => STACKED FINFET EEPROM [patent_app_type] => utility [patent_app_number] => 15/825678 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825678 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825678
Stacked FinFET EEPROM Nov 28, 2017 Issued
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