Search

Dipakkumar B. Gandhi

Examiner (ID: 16028, Phone: (571)272-3822 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2133, 2111, 2117, 2138
Total Applications
939
Issued Applications
765
Pending Applications
18
Abandoned Applications
156

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11124163 [patent_doc_number] => 20160321137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'ERROR PROTECTION KEY GENERATION METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/073807 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073807
Error protection key generation method and system Mar 17, 2016 Issued
Array ( [id] => 11966877 [patent_doc_number] => 20170271030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'METHOD AND SYSTEM FOR USING DOWNGRADED FLASH DIE FOR CACHE APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 15/074961 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15074961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/074961
METHOD AND SYSTEM FOR USING DOWNGRADED FLASH DIE FOR CACHE APPLICATIONS Mar 17, 2016 Abandoned
Array ( [id] => 13809189 [patent_doc_number] => 10181864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Methods and apparatus for performing reed-solomon encoding [patent_app_type] => utility [patent_app_number] => 15/054395 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5309 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/054395
Methods and apparatus for performing reed-solomon encoding Feb 25, 2016 Issued
Array ( [id] => 14427149 [patent_doc_number] => 10318378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Redundant array of independent NAND for a three-dimensional memory array [patent_app_type] => utility [patent_app_number] => 15/053719 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 7137 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053719
Redundant array of independent NAND for a three-dimensional memory array Feb 24, 2016 Issued
Array ( [id] => 11080184 [patent_doc_number] => 20160277149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'SPC SENSOR INTERFACE WITH PARTIAL PARITY PROTECTION' [patent_app_type] => utility [patent_app_number] => 15/052569 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9813 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052569
SPC sensor interface with partial parity protection Feb 23, 2016 Issued
Array ( [id] => 13863675 [patent_doc_number] => 10193576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Memory system and memory device [patent_app_type] => utility [patent_app_number] => 15/052010 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12365 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052010
Memory system and memory device Feb 23, 2016 Issued
Array ( [id] => 11264965 [patent_doc_number] => 09489262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Low density parity check encoder having length of 16200 and code rate of 2/15, and low density parity check encoding method using the same' [patent_app_type] => utility [patent_app_number] => 15/018762 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5703 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/018762
Low density parity check encoder having length of 16200 and code rate of 2/15, and low density parity check encoding method using the same Feb 7, 2016 Issued
Array ( [id] => 13202985 [patent_doc_number] => 10116420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Error retransmission mechanism-comprised methods, apparatuses and systems for transmitting and receiving visible light signal [patent_app_type] => utility [patent_app_number] => 15/011553 [patent_app_country] => US [patent_app_date] => 2016-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8726 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011553 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011553
Error retransmission mechanism-comprised methods, apparatuses and systems for transmitting and receiving visible light signal Jan 29, 2016 Issued
Array ( [id] => 11358476 [patent_doc_number] => 09535123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Frequency scaled segmented scan chain for integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/985699 [patent_app_country] => US [patent_app_date] => 2015-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6389 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14985699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/985699
Frequency scaled segmented scan chain for integrated circuits Dec 30, 2015 Issued
Array ( [id] => 15548935 [patent_doc_number] => 10574263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Method for implementing turbo equalization compensation, turbo equalizer and system [patent_app_type] => utility [patent_app_number] => 14/984351 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6833 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984351 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984351
Method for implementing turbo equalization compensation, turbo equalizer and system Dec 29, 2015 Issued
Array ( [id] => 12101051 [patent_doc_number] => 09858146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Reducing latency for raid destage operations' [patent_app_type] => utility [patent_app_number] => 14/976693 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6386 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976693 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/976693
Reducing latency for raid destage operations Dec 20, 2015 Issued
Array ( [id] => 11708035 [patent_doc_number] => 20170176534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'SELF-CHARACTERIZING HIGH-SPEED COMMUNICATION INTERFACES' [patent_app_type] => utility [patent_app_number] => 14/975691 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975691 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975691
SELF-CHARACTERIZING HIGH-SPEED COMMUNICATION INTERFACES Dec 17, 2015 Abandoned
Array ( [id] => 11711480 [patent_doc_number] => 20170179979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Systems and Methods for Minimum Storage Regeneration Erasure Code Construction Using r-Ary Trees' [patent_app_type] => utility [patent_app_number] => 14/974799 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974799 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974799
Systems and Methods for Minimum Storage Regeneration Erasure Code Construction Using r-Ary Trees Dec 17, 2015 Abandoned
Array ( [id] => 14457659 [patent_doc_number] => 10324790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-18 [patent_title] => Flexible data storage device mapping for data storage systems [patent_app_type] => utility [patent_app_number] => 14/973716 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973716 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973716
Flexible data storage device mapping for data storage systems Dec 16, 2015 Issued
Array ( [id] => 13240857 [patent_doc_number] => 10133627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Memory device controller with mirrored command and operating method thereof [patent_app_type] => utility [patent_app_number] => 14/966685 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9839 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14966685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/966685
Memory device controller with mirrored command and operating method thereof Dec 10, 2015 Issued
Array ( [id] => 10824666 [patent_doc_number] => 20160170832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'COMPUTING SYSTEM WITH SHIFT DATA PROTECTION MECHANISM AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/965779 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9400 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965779 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/965779
Computing system with shift data protection mechanism and method of operation thereof Dec 9, 2015 Issued
Array ( [id] => 11465728 [patent_doc_number] => 09582359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Write mapping to mitigate hard errors via soft-decision decoding' [patent_app_type] => utility [patent_app_number] => 14/963723 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963723 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963723
Write mapping to mitigate hard errors via soft-decision decoding Dec 8, 2015 Issued
Array ( [id] => 11266540 [patent_doc_number] => 09490849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-08 [patent_title] => 'Systems and methods for configuring product codes for error correction in a hard disk drive' [patent_app_type] => utility [patent_app_number] => 14/961274 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961274 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/961274
Systems and methods for configuring product codes for error correction in a hard disk drive Dec 6, 2015 Issued
Array ( [id] => 10726380 [patent_doc_number] => 20160072528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING PACKET IN BROADCASTING AND COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/942381 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 12106 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942381 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942381
Apparatus and method for transmitting and receiving packet in broadcasting and communication system Nov 15, 2015 Issued
Array ( [id] => 11621868 [patent_doc_number] => 20170132055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Determining Physical Layer Error Signatures of a Communications Link' [patent_app_type] => utility [patent_app_number] => 14/938819 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938819 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/938819
Determining Physical Layer Error Signatures of a Communications Link Nov 10, 2015 Abandoned
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