Search

Dipakkumar B. Gandhi

Examiner (ID: 6989, Phone: (571)272-3822 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2138, 2117, 2133, 2111
Total Applications
939
Issued Applications
765
Pending Applications
18
Abandoned Applications
156

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15377579 [patent_doc_number] => 10530524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Method and device for recovering error without retransmission of data frame in wireless LAN [patent_app_type] => utility [patent_app_number] => 15/532049 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 22052 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15532049 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/532049
Method and device for recovering error without retransmission of data frame in wireless LAN May 18, 2015 Issued
Array ( [id] => 12174655 [patent_doc_number] => 09892802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Hardware assisted scheme for testing memories using scan' [patent_app_type] => utility [patent_app_number] => 14/714381 [patent_app_country] => US [patent_app_date] => 2015-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4737 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14714381 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/714381
Hardware assisted scheme for testing memories using scan May 17, 2015 Issued
Array ( [id] => 14491631 [patent_doc_number] => 10332613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Nonvolatile memory system with retention monitor [patent_app_type] => utility [patent_app_number] => 14/715403 [patent_app_country] => US [patent_app_date] => 2015-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6590 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 646 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14715403 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/715403
Nonvolatile memory system with retention monitor May 17, 2015 Issued
Array ( [id] => 11884476 [patent_doc_number] => 09755667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-05 [patent_title] => 'Methods and systems for parallelizing high throughput iterative decoders' [patent_app_type] => utility [patent_app_number] => 14/712465 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712465 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/712465
Methods and systems for parallelizing high throughput iterative decoders May 13, 2015 Issued
Array ( [id] => 11056266 [patent_doc_number] => 20160253228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'ERROR DETECTION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/711491 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14711491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/711491
Error detection circuit and semiconductor apparatus using the same May 12, 2015 Issued
Array ( [id] => 10157555 [patent_doc_number] => 09189334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Memory management system and method' [patent_app_type] => utility [patent_app_number] => 14/707782 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12569 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14707782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/707782
Memory management system and method May 7, 2015 Issued
Array ( [id] => 11064414 [patent_doc_number] => 20160261377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'PACKET TRANSMISSION METHOD' [patent_app_type] => utility [patent_app_number] => 14/706942 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4470 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706942 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706942
Packet transmission method May 6, 2015 Issued
Array ( [id] => 11754161 [patent_doc_number] => 09712188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Decoding data stored with three orthogonal codewords' [patent_app_type] => utility [patent_app_number] => 14/703756 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 14720 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14703756 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/703756
Decoding data stored with three orthogonal codewords May 3, 2015 Issued
Array ( [id] => 11124161 [patent_doc_number] => 20160321135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/699810 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699810 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/699810
MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME Apr 28, 2015 Abandoned
Array ( [id] => 11020919 [patent_doc_number] => 20160217873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'POST PACKAGE REPAIR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/698617 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14698617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/698617
Post package repair device Apr 27, 2015 Issued
Array ( [id] => 11104457 [patent_doc_number] => 20160301428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'METHOD AND APPARATUS FOR SELECTIVE AND POWER-AWARE MEMORY ERROR PROTECTION AND MEMORY MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/684368 [patent_app_country] => US [patent_app_date] => 2015-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684368 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/684368
Method and apparatus for selective and power-aware memory error protection and memory management Apr 10, 2015 Issued
Array ( [id] => 10731791 [patent_doc_number] => 20160077940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'MEMORY DEVICE CAPABLE OF QUICKLY REPAIRING FAIL CELL' [patent_app_type] => utility [patent_app_number] => 14/683705 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21632 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683705 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/683705
Memory device capable of quickly repairing fail cell Apr 9, 2015 Issued
Array ( [id] => 11221017 [patent_doc_number] => 09449358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Arrangements for increasing detection confidence' [patent_app_type] => utility [patent_app_number] => 14/681574 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3383 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681574 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/681574
Arrangements for increasing detection confidence Apr 7, 2015 Issued
Array ( [id] => 12047170 [patent_doc_number] => 09824778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Nonvolatile memory system and data recovery method thereof' [patent_app_type] => utility [patent_app_number] => 14/674975 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 13354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14674975 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/674975
Nonvolatile memory system and data recovery method thereof Mar 30, 2015 Issued
Array ( [id] => 11802151 [patent_doc_number] => 09543042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 14/673333 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7558 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673333 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673333
Semiconductor memory apparatus Mar 29, 2015 Issued
Array ( [id] => 14921787 [patent_doc_number] => 10432228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 4096-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 14/671576 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6585 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 435 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/671576
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 4096-symbol mapping, and bit interleaving method using same Mar 26, 2015 Issued
Array ( [id] => 10385846 [patent_doc_number] => 20150270854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME' [patent_app_type] => utility [patent_app_number] => 14/664712 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6942 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14664712 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/664712
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 1024-symbol mapping, and bit interleaving method using same Mar 19, 2015 Issued
Array ( [id] => 13120385 [patent_doc_number] => 10078546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Temperature related error management [patent_app_type] => utility [patent_app_number] => 14/644365 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 10697 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14644365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/644365
Temperature related error management Mar 10, 2015 Issued
Array ( [id] => 11044307 [patent_doc_number] => 20160241263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME' [patent_app_type] => utility [patent_app_number] => 14/639646 [patent_app_country] => US [patent_app_date] => 2015-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6904 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/639646
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same Mar 4, 2015 Issued
Array ( [id] => 11510963 [patent_doc_number] => 09602136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same' [patent_app_type] => utility [patent_app_number] => 14/636053 [patent_app_country] => US [patent_app_date] => 2015-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6979 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636053 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/636053
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same Mar 1, 2015 Issued
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