Search

Dipakkumar B. Gandhi

Examiner (ID: 6989, Phone: (571)272-3822 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2138, 2117, 2133, 2111
Total Applications
939
Issued Applications
765
Pending Applications
18
Abandoned Applications
156

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10342414 [patent_doc_number] => 20150227419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'ERROR CORRECTION DECODER BASED ON LOG-LIKELIHOOD RATIO DATA' [patent_app_type] => utility [patent_app_number] => 14/308985 [patent_app_country] => US [patent_app_date] => 2014-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 15023 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308985 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/308985
ERROR CORRECTION DECODER BASED ON LOG-LIKELIHOOD RATIO DATA Jun 18, 2014 Abandoned
Array ( [id] => 9795050 [patent_doc_number] => 20150006994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH MULTIPLE SUB-MEMORY CELL ARRAYS AND MEMORY SYSTEM INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 14/300289 [patent_app_country] => US [patent_app_date] => 2014-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5531 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14300289 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/300289
Semiconductor memory device with multiple sub-memory cell arrays and memory system including same Jun 9, 2014 Issued
Array ( [id] => 10464903 [patent_doc_number] => 20150349919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'RADIO DATA PACKETS' [patent_app_type] => utility [patent_app_number] => 14/290244 [patent_app_country] => US [patent_app_date] => 2014-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5605 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14290244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/290244
RADIO DATA PACKETS May 28, 2014 Abandoned
Array ( [id] => 10941617 [patent_doc_number] => 20140344638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND COMMUNICATION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/279071 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8008 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279071 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/279071
SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND COMMUNICATION DEVICE May 14, 2014 Abandoned
Array ( [id] => 10433858 [patent_doc_number] => 20150318870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'VARIABLE WIDTH ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/265907 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265907 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265907
Variable width error correction Apr 29, 2014 Issued
Array ( [id] => 10285767 [patent_doc_number] => 20150170765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'APPARATUS AND METHOD FOR DECODING DATA' [patent_app_type] => utility [patent_app_number] => 14/254659 [patent_app_country] => US [patent_app_date] => 2014-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14254659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/254659
Apparatus and method for decoding data Apr 15, 2014 Issued
Array ( [id] => 14601157 [patent_doc_number] => 10353771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-16 [patent_title] => Managing data storage [patent_app_type] => utility [patent_app_number] => 14/230583 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6241 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230583 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230583
Managing data storage Mar 30, 2014 Issued
Array ( [id] => 10914451 [patent_doc_number] => 20140317470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/225686 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 33739 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225686 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/225686
Memory devices that perform masked write operations and methods of operating the same Mar 25, 2014 Issued
Array ( [id] => 9933935 [patent_doc_number] => 20150082127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'MANAGING QUALITY OF SERVICE FOR COMMUNICATION SESSIONS' [patent_app_type] => utility [patent_app_number] => 14/219633 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8229 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219633 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219633
Managing quality of service for communication sessions Mar 18, 2014 Issued
Array ( [id] => 9746116 [patent_doc_number] => 20140281836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD AND SYSTEM FOR PROVIDING ERROR CORRECTION TO LOW-LATENCY STREAMING VIDEO' [patent_app_type] => utility [patent_app_number] => 14/204385 [patent_app_country] => US [patent_app_date] => 2014-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4643 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14204385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/204385
Method and system for providing error correction to low-latency streaming video Mar 10, 2014 Issued
Array ( [id] => 10564215 [patent_doc_number] => 09287898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Method and circuit for shortening latency of Chien\'S search algorithm for BCH codewords' [patent_app_type] => utility [patent_app_number] => 14/200570 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5201 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200570
Method and circuit for shortening latency of Chien'S search algorithm for BCH codewords Mar 6, 2014 Issued
Array ( [id] => 10590372 [patent_doc_number] => 09311992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Decoding system and method for electronic non-volatile computer storage apparatus' [patent_app_type] => utility [patent_app_number] => 14/200659 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200659
Decoding system and method for electronic non-volatile computer storage apparatus Mar 6, 2014 Issued
Array ( [id] => 11228177 [patent_doc_number] => 09455905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Encapsulation for link layer preemption' [patent_app_type] => utility [patent_app_number] => 14/187098 [patent_app_country] => US [patent_app_date] => 2014-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187098
Encapsulation for link layer preemption Feb 20, 2014 Issued
Array ( [id] => 9658784 [patent_doc_number] => 20140229789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'LDPC DESIGN FOR HIGH PARALLELISM, LOW ERROR FLOOR, AND SIMPLE ENCODING' [patent_app_type] => utility [patent_app_number] => 14/179942 [patent_app_country] => US [patent_app_date] => 2014-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7220 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179942 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/179942
LDPC design for high parallelism, low error floor, and simple encoding Feb 12, 2014 Issued
Array ( [id] => 12948742 [patent_doc_number] => 09835684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => In-circuit test structure for printed circuit board [patent_app_type] => utility [patent_app_number] => 14/175392 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14175392 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/175392
In-circuit test structure for printed circuit board Feb 6, 2014 Issued
Array ( [id] => 9746077 [patent_doc_number] => 20140281796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'STORAGE CONTROL APPARATUS AND STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/174894 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 19981 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174894
Storage control apparatus and storage system Feb 6, 2014 Issued
Array ( [id] => 14431201 [patent_doc_number] => 10320420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Bit-flip coding [patent_app_type] => utility [patent_app_number] => 15/112013 [patent_app_country] => US [patent_app_date] => 2014-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7647 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15112013 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/112013
Bit-flip coding Jan 23, 2014 Issued
Array ( [id] => 11284856 [patent_doc_number] => 09500706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support' [patent_app_type] => utility [patent_app_number] => 14/161348 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161348 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161348
Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support Jan 21, 2014 Issued
Array ( [id] => 10847796 [patent_doc_number] => 08874997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-28 [patent_title] => 'System and method for combining pilot data with user data using a control module external to a memory' [patent_app_type] => utility [patent_app_number] => 14/158219 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 9023 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158219
System and method for combining pilot data with user data using a control module external to a memory Jan 16, 2014 Issued
Array ( [id] => 10292321 [patent_doc_number] => 20150177320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'SEMICONDUCTOR CHIP, STACK CHIP INCLUDING THE SAME, AND TESTING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/158117 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158117
Semiconductor chip, stack chip including the same, and testing method thereof Jan 16, 2014 Issued
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