Dirk Wright

Array ( [id] => 4073129 [patent_doc_number] => 05896316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Semiconductor non-volatile programmable memory device preventing non-selected memory cells from disturb during programmable operation' [patent_app_type] => 1 [patent_app_number] => 9/150189 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5235 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896316.pdf [firstpage_image] =>[orig_patent_app_number] => 150189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247465 [patent_doc_number] => 06118716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus for an address triggered RAM circuit' [patent_app_type] => 1 [patent_app_number] => 9/150389 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7669 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118716.pdf [firstpage_image] =>[orig_patent_app_number] => 150389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3940299 [patent_doc_number] => 05953269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and apparatus for remapping addresses for redundancy' [patent_app_type] => 1 [patent_app_number] => 9/146586 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4339 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953269.pdf [firstpage_image] =>[orig_patent_app_number] => 146586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3947027 [patent_doc_number] => 05940319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Magnetic random access memory and fabricating method thereof' [patent_app_type] => 1 [patent_app_number] => 9/144686 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3920 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940319.pdf [firstpage_image] =>[orig_patent_app_number] => 144686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4283072 [patent_doc_number] => 06307775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Deaprom and transistor with gallium nitride or gallium aluminum nitride gate' [patent_app_type] => 1 [patent_app_number] => 9/140978 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7410 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307775.pdf [firstpage_image] =>[orig_patent_app_number] => 140978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998748 [patent_doc_number] => 05959932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method and apparatus for detecting errors in the writing of data to a memory' [patent_app_type] => 1 [patent_app_number] => 9/135290 [patent_app_country] => US [patent_app_date] => 1998-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 8245 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959932.pdf [firstpage_image] =>[orig_patent_app_number] => 135290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4245900 [patent_doc_number] => 06075720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Memory cell for DRAM embedded in logic' [patent_app_type] => 1 [patent_app_number] => 9/134488 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3084 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075720.pdf [firstpage_image] =>[orig_patent_app_number] => 134488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4045684 [patent_doc_number] => 05943261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for programming a flash memory' [patent_app_type] => 1 [patent_app_number] => 9/130889 [patent_app_country] => US [patent_app_date] => 1998-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5751 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943261.pdf [firstpage_image] =>[orig_patent_app_number] => 130889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998240 [patent_doc_number] => 05959898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Dynamic cell plate sensing and equilibration in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/129144 [patent_app_country] => US [patent_app_date] => 1998-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3232 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959898.pdf [firstpage_image] =>[orig_patent_app_number] => 129144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915358 [patent_doc_number] => 05898627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Semiconductor memory having redundant memory cell array' [patent_app_type] => 1 [patent_app_number] => 9/115688 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8108 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898627.pdf [firstpage_image] =>[orig_patent_app_number] => 115688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153180 [patent_doc_number] => 06061291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Memory integrated circuit supporting maskable block write operation and arbitrary redundant column repair' [patent_app_type] => 1 [patent_app_number] => 9/115379 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4292 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061291.pdf [firstpage_image] =>[orig_patent_app_number] => 115379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950796 [patent_doc_number] => 05930194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor memory device capable of block writing in large bus width' [patent_app_type] => 1 [patent_app_number] => 9/109089 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9516 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930194.pdf [firstpage_image] =>[orig_patent_app_number] => 109089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4025875 [patent_doc_number] => 05963481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Embedded enhanced DRAM, and associated method' [patent_app_type] => 1 [patent_app_number] => 9/108089 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3246 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963481.pdf [firstpage_image] =>[orig_patent_app_number] => 108089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3896325 [patent_doc_number] => 05894438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Method for programming and erasing a memory cell of a flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/105589 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1614 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894438.pdf [firstpage_image] =>[orig_patent_app_number] => 105589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054406 [patent_doc_number] => 05912839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Universal memory element and method of programming same' [patent_app_type] => 1 [patent_app_number] => 9/102887 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 14792 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912839.pdf [firstpage_image] =>[orig_patent_app_number] => 102887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4011894 [patent_doc_number] => 05986926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Identification element and method of manufacturing an identification element' [patent_app_type] => 1 [patent_app_number] => 9/102278 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2086 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986926.pdf [firstpage_image] =>[orig_patent_app_number] => 102278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970130 [patent_doc_number] => 05936894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Dual level wordline clamp for reduced memory cell current' [patent_app_type] => 1 [patent_app_number] => 9/094786 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936894.pdf [firstpage_image] =>[orig_patent_app_number] => 094786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4046120 [patent_doc_number] => 05943290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Apparatus for providing a quiet time before analog signal sampling in a mixed signal integrated circuit employing synchronous and asynchronous clocking' [patent_app_type] => 1 [patent_app_number] => 9/096787 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5382 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943290.pdf [firstpage_image] =>[orig_patent_app_number] => 096787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4086405 [patent_doc_number] => 05966339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Programmable/reprogrammable fuse' [patent_app_type] => 1 [patent_app_number] => 9/088889 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4717 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966339.pdf [firstpage_image] =>[orig_patent_app_number] => 088889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915108 [patent_doc_number] => 05898609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Ferroelectric memory having circuit for discharging pyroelectric charges' [patent_app_type] => 1 [patent_app_number] => 9/086489 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2419 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898609.pdf [firstpage_image] =>[orig_patent_app_number] => 086489 [rel_patent_id] =>[rel_patent_doc_number] =>)