Dirk Wright

Array ( [id] => 3960070 [patent_doc_number] => 05991188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Non-volatile ferroelectric memory with section plate line drivers and method for accessing the same' [patent_app_type] => 1 [patent_app_number] => 9/084390 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7162 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991188.pdf [firstpage_image] =>[orig_patent_app_number] => 084390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4093561 [patent_doc_number] => 06055196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Semiconductor device with increased replacement efficiency by redundant memory cell arrays' [patent_app_type] => 1 [patent_app_number] => 9/084107 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4236 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055196.pdf [firstpage_image] =>[orig_patent_app_number] => 084107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4219406 [patent_doc_number] => 06028806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Semiconductor memory with local phase generation from global phase signals and local isolation signals' [patent_app_type] => 1 [patent_app_number] => 9/083606 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028806.pdf [firstpage_image] =>[orig_patent_app_number] => 083606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4217143 [patent_doc_number] => 06078547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method and structure for controlling operation of a DRAM array' [patent_app_type] => 1 [patent_app_number] => 9/076608 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2207 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078547.pdf [firstpage_image] =>[orig_patent_app_number] => 076608 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998066 [patent_doc_number] => 05959888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Non-volatile semiconductor memory device and method of manufacturing non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/072987 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 66 [patent_no_of_words] => 7696 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959888.pdf [firstpage_image] =>[orig_patent_app_number] => 072987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4082325 [patent_doc_number] => 06069818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Semiconductor memory device having storage nodes doped with first and second type impurities' [patent_app_type] => 1 [patent_app_number] => 9/069206 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3702 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069818.pdf [firstpage_image] =>[orig_patent_app_number] => 069206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131243 [patent_doc_number] => 06072727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Dynamic sense amplifier for EPROM, EEPROM and flash-EPROM memory devices' [patent_app_type] => 1 [patent_app_number] => 9/070105 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3972 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072727.pdf [firstpage_image] =>[orig_patent_app_number] => 070105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110461 [patent_doc_number] => 06097648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Semiconductor memory device having plurality of equalizer control line drivers' [patent_app_type] => 1 [patent_app_number] => 9/066579 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097648.pdf [firstpage_image] =>[orig_patent_app_number] => 066579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1488629 [patent_doc_number] => 06366517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Semiconductor integrated circuit capable of readily adjusting circuit characteristic' [patent_app_type] => B1 [patent_app_number] => 09/062590 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3254 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366517.pdf [firstpage_image] =>[orig_patent_app_number] => 09062590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3986654 [patent_doc_number] => 05905690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Synchronous semiconductor device having circuitry capable of surely resetting test mode' [patent_app_type] => 1 [patent_app_number] => 9/058987 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12367 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905690.pdf [firstpage_image] =>[orig_patent_app_number] => 058987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144780 [patent_doc_number] => 06016278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Failure analysis method and device' [patent_app_type] => 1 [patent_app_number] => 9/055905 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 36 [patent_no_of_words] => 8375 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016278.pdf [firstpage_image] =>[orig_patent_app_number] => 055905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4096884 [patent_doc_number] => 06026030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Structure for echo IC' [patent_app_type] => 1 [patent_app_number] => 9/054504 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2022 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026030.pdf [firstpage_image] =>[orig_patent_app_number] => 054504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110562 [patent_doc_number] => 06097655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Pull through FIFO memory device' [patent_app_type] => 1 [patent_app_number] => 9/055002 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2721 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097655.pdf [firstpage_image] =>[orig_patent_app_number] => 055002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953087 [patent_doc_number] => 05973953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Semiconductor memory device having improved bit line structure' [patent_app_type] => 1 [patent_app_number] => 9/038278 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 7533 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973953.pdf [firstpage_image] =>[orig_patent_app_number] => 038278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4097108 [patent_doc_number] => 06026045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Semiconductor memory device having multibank' [patent_app_type] => 1 [patent_app_number] => 9/035678 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5327 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026045.pdf [firstpage_image] =>[orig_patent_app_number] => 035678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3963839 [patent_doc_number] => 05978264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Nonvolatile semiconductor memory device operable at high speed with low power supply voltage while suppressing increase of chip area' [patent_app_type] => 1 [patent_app_number] => 9/033580 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 68 [patent_no_of_words] => 18887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 453 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978264.pdf [firstpage_image] =>[orig_patent_app_number] => 033580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4064142 [patent_doc_number] => 05933363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Associative memory having comparator for detecting data match signal' [patent_app_type] => 1 [patent_app_number] => 9/017204 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4798 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933363.pdf [firstpage_image] =>[orig_patent_app_number] => 017204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960586 [patent_doc_number] => 05991221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Microcomputer and microprocessor having flash memory operable from single external power supply' [patent_app_type] => 1 [patent_app_number] => 9/016300 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 14113 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991221.pdf [firstpage_image] =>[orig_patent_app_number] => 016300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4086233 [patent_doc_number] => 05966327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'On-off current ratio improving circuit for flat-cell array' [patent_app_type] => 1 [patent_app_number] => 9/014405 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5175 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966327.pdf [firstpage_image] =>[orig_patent_app_number] => 014405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054475 [patent_doc_number] => 05912844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method for flash EEPROM data writing' [patent_app_type] => 1 [patent_app_number] => 9/015606 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912844.pdf [firstpage_image] =>[orig_patent_app_number] => 015606 [rel_patent_id] =>[rel_patent_doc_number] =>)