
Dirk Wright
Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )
| Most Active Art Unit | 3502 |
| Art Unit(s) | 3502, 3656, 3659, 3622, 3655, 2899, 3681 |
| Total Applications | 4396 |
| Issued Applications | 4127 |
| Pending Applications | 57 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3962591
[patent_doc_number] => 05999479
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Row decoder for nonvolatile memory having a low-voltage power supply'
[patent_app_type] => 1
[patent_app_number] => 9/010202
[patent_app_country] => US
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[pdf_file] => patents/05/999/05999479.pdf
[firstpage_image] =>[orig_patent_app_number] => 010202
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Array
(
[id] => 3963809
[patent_doc_number] => 05978262
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[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Circuit and method of latching a bit line in a non-volatile memory'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/009290 | Circuit and method of latching a bit line in a non-volatile memory | Jan 19, 1998 | Issued |
| 09/009402 | SYCHRONOUS MEMORY BURN-IN METHOD | Jan 19, 1998 | Issued |
Array
(
[id] => 3946955
[patent_doc_number] => 05940314
[patent_country] => US
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[patent_issue_date] => 1999-08-17
[patent_title] => 'Ultra-high density memory device'
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Array
(
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[patent_doc_number] => 05949727
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[patent_issue_date] => 1999-09-07
[patent_title] => 'Semiconductor memory device with data sensing scheme regardless of bit line coupling'
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[patent_app_date] => 1998-01-13
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Array
(
[id] => 3960748
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Internal clock generation circuit for synchronous semiconductor device'
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/004000 | Internal clock generation circuit for synchronous semiconductor device | Jan 7, 1998 | Issued |
Array
(
[id] => 4086464
[patent_doc_number] => 05966343
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[patent_issue_date] => 1999-10-12
[patent_title] => 'Variable latency memory circuit'
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[firstpage_image] =>[orig_patent_app_number] => 996522
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/996522 | Variable latency memory circuit | Dec 22, 1997 | Issued |
Array
(
[id] => 4217115
[patent_doc_number] => 06078545
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[patent_issue_date] => 2000-06-20
[patent_title] => 'Data transfer circuit'
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[pdf_file] => patents/06/078/06078545.pdf
[firstpage_image] =>[orig_patent_app_number] => 995520
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/995520 | Data transfer circuit | Dec 21, 1997 | Issued |
Array
(
[id] => 4284678
[patent_doc_number] => 06246602
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[patent_kind] => NA
[patent_issue_date] => 2001-06-12
[patent_title] => 'Ferroelectric storage device'
[patent_app_type] => 1
[patent_app_number] => 8/995025
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[pdf_file] => patents/06/246/06246602.pdf
[firstpage_image] =>[orig_patent_app_number] => 995025
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/995025 | Ferroelectric storage device | Dec 18, 1997 | Issued |
Array
(
[id] => 3950360
[patent_doc_number] => 05930163
[patent_country] => US
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[patent_issue_date] => 1999-07-27
[patent_title] => 'Semiconductor memory device having two P-well layout structure'
[patent_app_type] => 1
[patent_app_number] => 8/993180
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[firstpage_image] =>[orig_patent_app_number] => 993180
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993180 | Semiconductor memory device having two P-well layout structure | Dec 17, 1997 | Issued |
Array
(
[id] => 3960193
[patent_doc_number] => 05991196
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[patent_issue_date] => 1999-11-23
[patent_title] => 'Reprogrammable memory device with variable page size'
[patent_app_type] => 1
[patent_app_number] => 8/991423
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[patent_app_date] => 1997-12-16
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[pdf_file] => patents/05/991/05991196.pdf
[firstpage_image] =>[orig_patent_app_number] => 991423
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991423 | Reprogrammable memory device with variable page size | Dec 15, 1997 | Issued |
Array
(
[id] => 3925293
[patent_doc_number] => 06002625
[patent_country] => US
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[patent_issue_date] => 1999-12-14
[patent_title] => 'Cell array and sense amplifier structure exhibiting improved noise characteristic and reduced size'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991618 | Cell array and sense amplifier structure exhibiting improved noise characteristic and reduced size | Dec 15, 1997 | Issued |
Array
(
[id] => 3932542
[patent_doc_number] => 05914897
[patent_country] => US
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[patent_issue_date] => 1999-06-22
[patent_title] => 'FIFO memory device having address detection portion'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990801 | FIFO memory device having address detection portion | Dec 14, 1997 | Issued |
Array
(
[id] => 4054487
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[patent_title] => 'Presettable static ram with read/write controller'
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[firstpage_image] =>[orig_patent_app_number] => 988100
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988100 | Presettable static ram with read/write controller | Dec 9, 1997 | Issued |
Array
(
[id] => 4054586
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[patent_title] => 'Multi-bit semiconductor memory device allowing efficient testing'
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Array
(
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[patent_title] => 'Semiconductor memory device with triple metal layer'
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Array
(
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[patent_title] => 'Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/986506 | Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations | Dec 7, 1997 | Issued |
Array
(
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/982204 | Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array | Nov 30, 1997 | Issued |