
Dirk Wright
Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )
| Most Active Art Unit | 3502 |
| Art Unit(s) | 3502, 3656, 3659, 3622, 3655, 2899, 3681 |
| Total Applications | 4396 |
| Issued Applications | 4127 |
| Pending Applications | 57 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4078048
[patent_doc_number] => 06009021
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'MOS logic circuit with hold operation'
[patent_app_type] => 1
[patent_app_number] => 8/956541
[patent_app_country] => US
[patent_app_date] => 1997-10-23
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[pdf_file] => patents/06/009/06009021.pdf
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Array
(
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[patent_issue_date] => 1999-11-23
[patent_title] => 'Input buffer circuit and method'
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Array
(
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[patent_issue_date] => 1998-12-22
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Array
(
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[patent_issue_date] => 1999-08-31
[patent_title] => 'Floating gate MOS transistor charge injection circuit and computation devices incorporating it'
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Array
(
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Array
(
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[patent_issue_date] => 1999-05-04
[patent_title] => 'Programmable reference voltage source, particularly for analog memories'
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Array
(
[id] => 4011840
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[patent_title] => 'Method of and apparatus for increasing load resistance within an SRAM array'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/941582 | Method of and apparatus for increasing load resistance within an SRAM array | Sep 29, 1997 | Issued |
Array
(
[id] => 3986358
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[patent_issue_date] => 1999-05-18
[patent_title] => 'Hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit and medium on which the hierarchical routing program is stored'
[patent_app_type] => 1
[patent_app_number] => 8/940005
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Array
(
[id] => 3940243
[patent_doc_number] => 05953265
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[patent_issue_date] => 1999-09-14
[patent_title] => 'Memory having error detection and correction'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/941509 | Memory having error detection and correction | Sep 28, 1997 | Issued |
Array
(
[id] => 3950666
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[patent_issue_date] => 1999-07-27
[patent_title] => 'Data retention test for static memory cell'
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Array
(
[id] => 3905063
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[patent_title] => 'Input/output buffer memory circuit capable of minimizing data transfer required in input and output buffering operations'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/938839 | Input/output buffer memory circuit capable of minimizing data transfer required in input and output buffering operations | Sep 25, 1997 | Issued |
Array
(
[id] => 4077841
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Array
(
[id] => 4054376
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[patent_title] => 'Method and system for testing and adjusting threshold voltages in flash eeproms'
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Array
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[patent_title] => 'Row address control circuits having a predecoding address sampling pulse generator and methods for memory devices'
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Array
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Array
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Array
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Array
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Array
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Array
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