Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6911086 [patent_doc_number] => 20050174844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Multi-bit-per-cell flash EEPROM memory with refresh' [patent_app_type] => utility [patent_app_number] => 11/101938 [patent_app_country] => US [patent_app_date] => 2005-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6934 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174844.pdf [firstpage_image] =>[orig_patent_app_number] => 11101938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/101938
Multi-bit-per-cell flash EEPROM memory with refresh Apr 6, 2005 Issued
Array ( [id] => 902604 [patent_doc_number] => 07339839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Triggering of IO equilibrating ending signal with firing of column access signal' [patent_app_type] => utility [patent_app_number] => 11/089382 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2938 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/339/07339839.pdf [firstpage_image] =>[orig_patent_app_number] => 11089382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089382
Triggering of IO equilibrating ending signal with firing of column access signal Mar 23, 2005 Issued
Array ( [id] => 538307 [patent_doc_number] => 07184356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/074801 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 45 [patent_no_of_words] => 34479 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/184/07184356.pdf [firstpage_image] =>[orig_patent_app_number] => 11074801 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/074801
Semiconductor memory device Mar 8, 2005 Issued
Array ( [id] => 5737363 [patent_doc_number] => 20060007753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Isolation control circuit and method for a memory device' [patent_app_type] => utility [patent_app_number] => 11/073765 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5742 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20060007753.pdf [firstpage_image] =>[orig_patent_app_number] => 11073765 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/073765
Isolation control circuit and method for a memory device Mar 7, 2005 Issued
Array ( [id] => 554196 [patent_doc_number] => 07164617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Memory control apparatus for synchronous memory unit with switched on/off clock signal' [patent_app_type] => utility [patent_app_number] => 11/073807 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 50 [patent_no_of_words] => 4950 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164617.pdf [firstpage_image] =>[orig_patent_app_number] => 11073807 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/073807
Memory control apparatus for synchronous memory unit with switched on/off clock signal Mar 7, 2005 Issued
Array ( [id] => 387514 [patent_doc_number] => 07304885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Phase change memories and/or methods of programming phase change memories using sequential reset control' [patent_app_type] => utility [patent_app_number] => 11/074557 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5816 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304885.pdf [firstpage_image] =>[orig_patent_app_number] => 11074557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/074557
Phase change memories and/or methods of programming phase change memories using sequential reset control Mar 7, 2005 Issued
Array ( [id] => 7245350 [patent_doc_number] => 20050141270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Nonvolatile memory device having circuit for stably supplying desired current during data writing' [patent_app_type] => utility [patent_app_number] => 11/063614 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12233 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141270.pdf [firstpage_image] =>[orig_patent_app_number] => 11063614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063614
Nonvolatile memory device having circuit for stably supplying desired current during data writing Feb 23, 2005 Issued
Array ( [id] => 647712 [patent_doc_number] => 07120054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Preconditioning global bitlines' [patent_app_type] => utility [patent_app_number] => 11/062661 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3046 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120054.pdf [firstpage_image] =>[orig_patent_app_number] => 11062661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062661
Preconditioning global bitlines Feb 21, 2005 Issued
Array ( [id] => 475489 [patent_doc_number] => 07230841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Content addressable memory having dynamic match resolution' [patent_app_type] => utility [patent_app_number] => 11/061259 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 12608 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230841.pdf [firstpage_image] =>[orig_patent_app_number] => 11061259 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061259
Content addressable memory having dynamic match resolution Feb 17, 2005 Issued
Array ( [id] => 459695 [patent_doc_number] => 07245549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Semiconductor memory device and method of controlling the semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/058302 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9167 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245549.pdf [firstpage_image] =>[orig_patent_app_number] => 11058302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058302
Semiconductor memory device and method of controlling the semiconductor memory device Feb 15, 2005 Issued
Array ( [id] => 5765078 [patent_doc_number] => 20060018162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Semiconductor memory device and method of controlling write sequence thereof' [patent_app_type] => utility [patent_app_number] => 11/058298 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5216 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20060018162.pdf [firstpage_image] =>[orig_patent_app_number] => 11058298 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058298
Semiconductor memory device and method of controlling write sequence thereof Feb 15, 2005 Issued
Array ( [id] => 459632 [patent_doc_number] => 07245533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Semiconductor memory device with reduced number of high-voltage transistors' [patent_app_type] => utility [patent_app_number] => 11/058192 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5322 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245533.pdf [firstpage_image] =>[orig_patent_app_number] => 11058192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058192
Semiconductor memory device with reduced number of high-voltage transistors Feb 15, 2005 Issued
Array ( [id] => 413299 [patent_doc_number] => 07283388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Memory device using multiple layer nano tube cell' [patent_app_type] => utility [patent_app_number] => 11/058184 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4879 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/283/07283388.pdf [firstpage_image] =>[orig_patent_app_number] => 11058184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058184
Memory device using multiple layer nano tube cell Feb 15, 2005 Issued
Array ( [id] => 507277 [patent_doc_number] => 07206216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Semiconductor device with a non-erasable memory and/or a nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/057682 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 33 [patent_no_of_words] => 17071 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206216.pdf [firstpage_image] =>[orig_patent_app_number] => 11057682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057682
Semiconductor device with a non-erasable memory and/or a nonvolatile memory Feb 14, 2005 Issued
Array ( [id] => 6965098 [patent_doc_number] => 20050231995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Nonvolatile ferroelectric memory device' [patent_app_type] => utility [patent_app_number] => 11/057192 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4859 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20050231995.pdf [firstpage_image] =>[orig_patent_app_number] => 11057192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057192
Nonvolatile ferroelectric memory device Feb 14, 2005 Issued
Array ( [id] => 624900 [patent_doc_number] => 07139185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'FeRAM having common main bit line' [patent_app_type] => utility [patent_app_number] => 11/057168 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5692 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139185.pdf [firstpage_image] =>[orig_patent_app_number] => 11057168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057168
FeRAM having common main bit line Feb 14, 2005 Issued
Array ( [id] => 5676566 [patent_doc_number] => 20060181921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method for writing data into memory and the control device' [patent_app_type] => utility [patent_app_number] => 11/056196 [patent_app_country] => US [patent_app_date] => 2005-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4455 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20060181921.pdf [firstpage_image] =>[orig_patent_app_number] => 11056196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/056196
Method for writing data into memory and the control device Feb 13, 2005 Issued
Array ( [id] => 5676555 [patent_doc_number] => 20060181910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Content addressable memory including a dual mode cycle boundary latch' [patent_app_type] => utility [patent_app_number] => 11/055830 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3799 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20060181910.pdf [firstpage_image] =>[orig_patent_app_number] => 11055830 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055830
Content addressable memory including a dual mode cycle boundary latch Feb 10, 2005 Issued
Array ( [id] => 5676596 [patent_doc_number] => 20060181951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method and apparatus for address generation' [patent_app_type] => utility [patent_app_number] => 11/056048 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2237 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20060181951.pdf [firstpage_image] =>[orig_patent_app_number] => 11056048 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/056048
Method and apparatus for address generation Feb 10, 2005 Issued
Array ( [id] => 554275 [patent_doc_number] => 07167385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Method and apparatus for controlling the timing of precharge in a content addressable memory system' [patent_app_type] => utility [patent_app_number] => 11/055802 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167385.pdf [firstpage_image] =>[orig_patent_app_number] => 11055802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055802
Method and apparatus for controlling the timing of precharge in a content addressable memory system Feb 10, 2005 Issued
Menu