Dirk Wright

Array ( [id] => 7109766 [patent_doc_number] => 20050207220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/898377 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 24784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20050207220.pdf [firstpage_image] =>[orig_patent_app_number] => 10898377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 674450 [patent_doc_number] => 07092297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-15 [patent_title] => 'Method for pulse erase in dual bit memory devices' [patent_app_type] => utility [patent_app_number] => 10/899684 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4554 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/092/07092297.pdf [firstpage_image] =>[orig_patent_app_number] => 10899684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 572791 [patent_doc_number] => 07158404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Power management circuit and memory cell' [patent_app_type] => utility [patent_app_number] => 10/899320 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2938 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/158/07158404.pdf [firstpage_image] =>[orig_patent_app_number] => 10899320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 754345 [patent_doc_number] => 07023750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Dynamical biasing of memory sense amplifiers' [patent_app_type] => utility [patent_app_number] => 10/898478 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4552 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023750.pdf [firstpage_image] =>[orig_patent_app_number] => 10898478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 732698 [patent_doc_number] => 07042766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-09 [patent_title] => 'Method of programming a flash memory device using multilevel charge storage' [patent_app_type] => utility [patent_app_number] => 10/896651 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4762 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042766.pdf [firstpage_image] =>[orig_patent_app_number] => 10896651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 689028 [patent_doc_number] => 07079423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-18 [patent_title] => 'Method for programming dual bit memory devices to reduce complementary bit disturbance' [patent_app_type] => utility [patent_app_number] => 10/896299 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/079/07079423.pdf [firstpage_image] =>[orig_patent_app_number] => 10896299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7244214 [patent_doc_number] => 20040257891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Self-repairing built-in self test for linked list memories' [patent_app_type] => new [patent_app_number] => 10/894126 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4463 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257891.pdf [firstpage_image] =>[orig_patent_app_number] => 10894126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 710510 [patent_doc_number] => 07061803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Method and device for preserving word line pass bias using ROM in NAND-type flash memory' [patent_app_type] => utility [patent_app_number] => 10/886867 [patent_app_country] => US [patent_app_date] => 2004-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5562 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061803.pdf [firstpage_image] =>[orig_patent_app_number] => 10886867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5054702 [patent_doc_number] => 20070057623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Electroluminescent optical recording medium' [patent_app_type] => utility [patent_app_number] => 10/559354 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3871 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057623.pdf [firstpage_image] =>[orig_patent_app_number] => 10559354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 678384 [patent_doc_number] => 07088610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Magnetic memory apparatus and method of manufacturing magnetic memory apparatus' [patent_app_type] => utility [patent_app_number] => 10/854215 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 15503 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088610.pdf [firstpage_image] =>[orig_patent_app_number] => 10854215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 554334 [patent_doc_number] => 07167388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Integrated circuit and method for operating an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/854928 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5827 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167388.pdf [firstpage_image] =>[orig_patent_app_number] => 10854928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7211423 [patent_doc_number] => 20050259474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'METHOD FOR PROGRAMMING SINGLE-BIT STORAGE SONOS TYPE MEMORY' [patent_app_type] => utility [patent_app_number] => 10/709666 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1974 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20050259474.pdf [firstpage_image] =>[orig_patent_app_number] => 10709666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7274278 [patent_doc_number] => 20040233729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor memory device and portable electronic apparatus including the same' [patent_app_type] => new [patent_app_number] => 10/847626 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 21859 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233729.pdf [firstpage_image] =>[orig_patent_app_number] => 10847626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7418845 [patent_doc_number] => 20040208050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'ROM embedded DRAM with anti-fuse programming' [patent_app_type] => new [patent_app_number] => 10/843161 [patent_app_country] => US [patent_app_date] => 2004-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5625 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20040208050.pdf [firstpage_image] =>[orig_patent_app_number] => 10843161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 486949 [patent_doc_number] => 07221596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'pFET nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 10/839985 [patent_app_country] => US [patent_app_date] => 2004-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 6740 [patent_no_of_claims] => 129 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221596.pdf [firstpage_image] =>[orig_patent_app_number] => 10839985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6904361 [patent_doc_number] => 20050099756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/833128 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20050099756.pdf [firstpage_image] =>[orig_patent_app_number] => 10833128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 678448 [patent_doc_number] => 07088628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Memory device and method of amplifying voltage levels of bit line and complementary bit line' [patent_app_type] => utility [patent_app_number] => 10/829133 [patent_app_country] => US [patent_app_date] => 2004-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7317 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088628.pdf [firstpage_image] =>[orig_patent_app_number] => 10829133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 882979 [patent_doc_number] => 07355880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-08 [patent_title] => 'Soft error resistant memory cell and method of manufacture' [patent_app_type] => utility [patent_app_number] => 10/823529 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 5871 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355880.pdf [firstpage_image] =>[orig_patent_app_number] => 10823529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7610473 [patent_doc_number] => 06842385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Automatic reference voltage regulation in a memory device' [patent_app_type] => utility [patent_app_number] => 10/817656 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5044 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842385.pdf [firstpage_image] =>[orig_patent_app_number] => 10817656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 762087 [patent_doc_number] => 07016240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-21 [patent_title] => 'Non-destructive memory read strobe pulse optimization training system' [patent_app_type] => utility [patent_app_number] => 10/809732 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3899 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016240.pdf [firstpage_image] =>[orig_patent_app_number] => 10809732 [rel_patent_id] =>[rel_patent_doc_number] =>)