
Dirk Wright
Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )
| Most Active Art Unit | 3502 |
| Art Unit(s) | 3502, 3656, 3659, 3622, 3655, 2899, 3681 |
| Total Applications | 4396 |
| Issued Applications | 4127 |
| Pending Applications | 57 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 573131
[patent_doc_number] => 07158429
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-01-02
[patent_title] => 'System for read path acceleration'
[patent_app_type] => utility
[patent_app_number] => 10/801432
[patent_app_country] => US
[patent_app_date] => 2004-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3249
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/158/07158429.pdf
[firstpage_image] =>[orig_patent_app_number] => 10801432
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/801432 | System for read path acceleration | Mar 15, 2004 | Issued |
Array
(
[id] => 684190
[patent_doc_number] => 07082056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-25
[patent_title] => 'Flash memory device and architecture with multi level cells'
[patent_app_type] => utility
[patent_app_number] => 10/800228
[patent_app_country] => US
[patent_app_date] => 2004-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 8239
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/082/07082056.pdf
[firstpage_image] =>[orig_patent_app_number] => 10800228
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/800228 | Flash memory device and architecture with multi level cells | Mar 11, 2004 | Issued |
Array
(
[id] => 5704117
[patent_doc_number] => 20060193165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-31
[patent_title] => 'Magnetoresistive element and magnetic memory device'
[patent_app_type] => utility
[patent_app_number] => 10/548830
[patent_app_country] => US
[patent_app_date] => 2004-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8437
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20060193165.pdf
[firstpage_image] =>[orig_patent_app_number] => 10548830
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/548830 | Magnetoresistive effect element and magnetic memory device | Mar 11, 2004 | Issued |
Array
(
[id] => 761962
[patent_doc_number] => 07016217
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-21
[patent_title] => 'Memory'
[patent_app_type] => utility
[patent_app_number] => 10/792926
[patent_app_country] => US
[patent_app_date] => 2004-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 65
[patent_no_of_words] => 23275
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/016/07016217.pdf
[firstpage_image] =>[orig_patent_app_number] => 10792926
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/792926 | Memory | Mar 4, 2004 | Issued |
Array
(
[id] => 7049586
[patent_doc_number] => 20050185473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Memory cell testing feature'
[patent_app_type] => utility
[patent_app_number] => 10/786511
[patent_app_country] => US
[patent_app_date] => 2004-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5119
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20050185473.pdf
[firstpage_image] =>[orig_patent_app_number] => 10786511
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/786511 | Memory cell testing feature | Feb 24, 2004 | Issued |
Array
(
[id] => 1070155
[patent_doc_number] => 06845032
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'Non-volatile latch circuit and a driving method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/785031
[patent_app_country] => US
[patent_app_date] => 2004-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10146
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/845/06845032.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785031
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785031 | Non-volatile latch circuit and a driving method thereof | Feb 24, 2004 | Issued |
Array
(
[id] => 7049561
[patent_doc_number] => 20050185448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'LOW LEAKAGE CURRENT STATIC RANDOM ACCESS MEMORY'
[patent_app_type] => utility
[patent_app_number] => 10/708328
[patent_app_country] => US
[patent_app_date] => 2004-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4251
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20050185448.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708328
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708328 | Low leakage current static random access memory | Feb 23, 2004 | Issued |
Array
(
[id] => 7134689
[patent_doc_number] => 20050180218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'VOLTAGE DISCHARGE TECHNIQUE FOR CONTROLLING THRESHOLD-VOLTAGE CHARACTERISTICS OF FLOATING-GATE TRANSISTOR IN CIRCUITRY SUCH AS FLASH EPROM'
[patent_app_type] => utility
[patent_app_number] => 10/780030
[patent_app_country] => US
[patent_app_date] => 2004-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 15849
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20050180218.pdf
[firstpage_image] =>[orig_patent_app_number] => 10780030
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/780030 | Voltage discharge technique for controlling threshold-voltage characteristics of floating-gate transistor in circuitry such as flash EPROM | Feb 16, 2004 | Issued |
Array
(
[id] => 7457508
[patent_doc_number] => 20040165466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'System and method for quick self-refresh exit with transitional refresh'
[patent_app_type] => new
[patent_app_number] => 10/781149
[patent_app_country] => US
[patent_app_date] => 2004-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5513
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0165/20040165466.pdf
[firstpage_image] =>[orig_patent_app_number] => 10781149
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/781149 | System and method for quick self-refresh exit with transitional refresh | Feb 16, 2004 | Issued |
Array
(
[id] => 7380178
[patent_doc_number] => 20040179420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Devices and methods for controlling active termination resistors in a memory system'
[patent_app_type] => new
[patent_app_number] => 10/777070
[patent_app_country] => US
[patent_app_date] => 2004-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6778
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20040179420.pdf
[firstpage_image] =>[orig_patent_app_number] => 10777070
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/777070 | Devices and methods for controlling active termination resistors in a memory system | Feb 12, 2004 | Issued |
Array
(
[id] => 693395
[patent_doc_number] => 07075840
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-07-11
[patent_title] => 'Low impedance memory bitline eliminating precharge'
[patent_app_type] => utility
[patent_app_number] => 10/779327
[patent_app_country] => US
[patent_app_date] => 2004-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2814
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/075/07075840.pdf
[firstpage_image] =>[orig_patent_app_number] => 10779327
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/779327 | Low impedance memory bitline eliminating precharge | Feb 12, 2004 | Issued |
Array
(
[id] => 7246570
[patent_doc_number] => 20040158690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Balanced sense amplifier control for open digit line architecture memory devices'
[patent_app_type] => new
[patent_app_number] => 10/775231
[patent_app_country] => US
[patent_app_date] => 2004-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4018
[patent_no_of_claims] => 73
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20040158690.pdf
[firstpage_image] =>[orig_patent_app_number] => 10775231
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/775231 | Balanced sense amplifier control for open digit line architecture memory devices | Feb 10, 2004 | Issued |
Array
(
[id] => 7293460
[patent_doc_number] => 20040213035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Sectored flash memory comprising means for controlling and for refreshing memory cells'
[patent_app_type] => new
[patent_app_number] => 10/775032
[patent_app_country] => US
[patent_app_date] => 2004-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7637
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0213/20040213035.pdf
[firstpage_image] =>[orig_patent_app_number] => 10775032
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/775032 | Sectored flash memory comprising means for controlling and for refreshing memory cells | Feb 8, 2004 | Issued |
Array
(
[id] => 952075
[patent_doc_number] => 06961282
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-01
[patent_title] => 'Semiconductor memory device with driving circuits for screening defective wordlines and related methods'
[patent_app_type] => utility
[patent_app_number] => 10/771930
[patent_app_country] => US
[patent_app_date] => 2004-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3452
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/961/06961282.pdf
[firstpage_image] =>[orig_patent_app_number] => 10771930
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/771930 | Semiconductor memory device with driving circuits for screening defective wordlines and related methods | Feb 3, 2004 | Issued |
Array
(
[id] => 682517
[patent_doc_number] => 07085176
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-08-01
[patent_title] => 'On-chip power-on voltage initialization'
[patent_app_type] => utility
[patent_app_number] => 10/771526
[patent_app_country] => US
[patent_app_date] => 2004-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3413
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085176.pdf
[firstpage_image] =>[orig_patent_app_number] => 10771526
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/771526 | On-chip power-on voltage initialization | Feb 3, 2004 | Issued |
Array
(
[id] => 7225331
[patent_doc_number] => 20040156222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Input stage apparatus and method having a variable reference voltage'
[patent_app_type] => new
[patent_app_number] => 10/770611
[patent_app_country] => US
[patent_app_date] => 2004-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4225
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20040156222.pdf
[firstpage_image] =>[orig_patent_app_number] => 10770611
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/770611 | Input stage apparatus and method having a variable reference voltage | Feb 1, 2004 | Issued |
Array
(
[id] => 7188374
[patent_doc_number] => 20050162797
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-28
[patent_title] => 'Systems and methods that employ inductive current steering for digital logic circuits'
[patent_app_type] => utility
[patent_app_number] => 10/766429
[patent_app_country] => US
[patent_app_date] => 2004-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8030
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20050162797.pdf
[firstpage_image] =>[orig_patent_app_number] => 10766429
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/766429 | Systems and methods that employ inductive current steering for digital logic circuits | Jan 27, 2004 | Issued |
Array
(
[id] => 7263500
[patent_doc_number] => 20040151049
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Memory cell with fuse element'
[patent_app_type] => new
[patent_app_number] => 10/764239
[patent_app_country] => US
[patent_app_date] => 2004-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4187
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20040151049.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764239
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764239 | Memory cell with fuse element | Jan 21, 2004 | Issued |
Array
(
[id] => 6989854
[patent_doc_number] => 20050088891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => '[DEVICE AND METHOD FOR BREAKING LEAKAGE CURRENT PATH OF MEMORY DEVICE AND STRUCTURE OF MEMORY DEVICE]'
[patent_app_type] => utility
[patent_app_number] => 10/707866
[patent_app_country] => US
[patent_app_date] => 2004-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4303
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20050088891.pdf
[firstpage_image] =>[orig_patent_app_number] => 10707866
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707866 | Device and method for breaking leakage current path of memory device and structure of memory device | Jan 19, 2004 | Issued |
Array
(
[id] => 7263476
[patent_doc_number] => 20040151027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Flash memory device with distributed coupling between array ground and substrate'
[patent_app_type] => new
[patent_app_number] => 10/758103
[patent_app_country] => US
[patent_app_date] => 2004-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5752
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20040151027.pdf
[firstpage_image] =>[orig_patent_app_number] => 10758103
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/758103 | Flash memory device with distributed coupling between array ground and substrate | Jan 15, 2004 | Issued |