Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1029532 [patent_doc_number] => 06882576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/615173 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4923 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882576.pdf [firstpage_image] =>[orig_patent_app_number] => 10615173 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615173
Semiconductor memory device Jul 8, 2003 Issued
Array ( [id] => 7352513 [patent_doc_number] => 20040013028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Repair circuit' [patent_app_type] => new [patent_app_number] => 10/615382 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3181 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20040013028.pdf [firstpage_image] =>[orig_patent_app_number] => 10615382 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615382
Repair circuit Jul 8, 2003 Issued
Array ( [id] => 1051652 [patent_doc_number] => 06862211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Magneto-resistive memory device' [patent_app_type] => utility [patent_app_number] => 10/614230 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4522 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862211.pdf [firstpage_image] =>[orig_patent_app_number] => 10614230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614230
Magneto-resistive memory device Jul 6, 2003 Issued
Array ( [id] => 7374721 [patent_doc_number] => 20040027878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Row decoder in flash memory and erase method of flash memory cell using the same' [patent_app_type] => new [patent_app_number] => 10/614229 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3524 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027878.pdf [firstpage_image] =>[orig_patent_app_number] => 10614229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614229
Row decoder in flash memory and erase method of flash memory cell using the same Jul 6, 2003 Issued
Array ( [id] => 7386127 [patent_doc_number] => 20040037116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Structure and operating method for nonvolatile memory cell' [patent_app_type] => new [patent_app_number] => 10/610881 [patent_app_country] => US [patent_app_date] => 2003-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3250 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037116.pdf [firstpage_image] =>[orig_patent_app_number] => 10610881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/610881
Structure and operating method for nonvolatile memory cell Jul 1, 2003 Issued
Array ( [id] => 7619099 [patent_doc_number] => 06944090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method and circuit for precise timing of signals in an embedded DRAM array' [patent_app_type] => utility [patent_app_number] => 10/604184 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5620 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944090.pdf [firstpage_image] =>[orig_patent_app_number] => 10604184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604184
Method and circuit for precise timing of signals in an embedded DRAM array Jun 29, 2003 Issued
Array ( [id] => 1032656 [patent_doc_number] => 06879533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Integrated circuit memory devices including active load circuits and related methods' [patent_app_type] => utility [patent_app_number] => 10/609071 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6166 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879533.pdf [firstpage_image] =>[orig_patent_app_number] => 10609071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609071
Integrated circuit memory devices including active load circuits and related methods Jun 26, 2003 Issued
Array ( [id] => 959425 [patent_doc_number] => 06954373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Apparatus and method for determining the logic state of a magnetic tunnel junction memory device' [patent_app_type] => utility [patent_app_number] => 10/609278 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7220 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954373.pdf [firstpage_image] =>[orig_patent_app_number] => 10609278 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609278
Apparatus and method for determining the logic state of a magnetic tunnel junction memory device Jun 26, 2003 Issued
Array ( [id] => 7415539 [patent_doc_number] => 20040264265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM' [patent_app_type] => new [patent_app_number] => 10/606584 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20040264265.pdf [firstpage_image] =>[orig_patent_app_number] => 10606584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/606584
Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM Jun 25, 2003 Issued
Array ( [id] => 1114787 [patent_doc_number] => 06804137 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Data storage medium having layers acting as transistor' [patent_app_type] => B1 [patent_app_number] => 10/461632 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3347 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804137.pdf [firstpage_image] =>[orig_patent_app_number] => 10461632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461632
Data storage medium having layers acting as transistor Jun 11, 2003 Issued
Array ( [id] => 7325205 [patent_doc_number] => 20040252544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Die customization using programmable resistance memory elements' [patent_app_type] => new [patent_app_number] => 10/459632 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4736 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20040252544.pdf [firstpage_image] =>[orig_patent_app_number] => 10459632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459632
Die customization using programmable resistance memory elements Jun 10, 2003 Issued
Array ( [id] => 7287913 [patent_doc_number] => 20040109377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Nonvolatile memory device having circuit for stably supplying desired current during data writing' [patent_app_type] => new [patent_app_number] => 10/456530 [patent_app_country] => US [patent_app_date] => 2003-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12417 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20040109377.pdf [firstpage_image] =>[orig_patent_app_number] => 10456530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/456530
Nonvolatile memory device having circuit for stably supplying desired current during data writing Jun 8, 2003 Issued
Array ( [id] => 1135671 [patent_doc_number] => 06788580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Nonvolatile semiconductor storage device and data erasing method' [patent_app_type] => B2 [patent_app_number] => 10/454630 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4765 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788580.pdf [firstpage_image] =>[orig_patent_app_number] => 10454630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454630
Nonvolatile semiconductor storage device and data erasing method Jun 4, 2003 Issued
Array ( [id] => 7278778 [patent_doc_number] => 20040061155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Ferroelectric memory with read-only memory cells, and fabrication method thereof' [patent_app_type] => new [patent_app_number] => 10/453484 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5734 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061155.pdf [firstpage_image] =>[orig_patent_app_number] => 10453484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453484
Ferroelectric memory with read-only memory cells, and fabrication method thereof Jun 3, 2003 Issued
Array ( [id] => 7360467 [patent_doc_number] => 20040004898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Dual port static memory cell and semiconductor memory device having the same' [patent_app_type] => new [patent_app_number] => 10/453030 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3947 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004898.pdf [firstpage_image] =>[orig_patent_app_number] => 10453030 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453030
Dual port static memory cell and semiconductor memory device having the same Jun 2, 2003 Issued
Array ( [id] => 7610498 [patent_doc_number] => 06842360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'High-density content addressable memory cell' [patent_app_type] => utility [patent_app_number] => 10/452230 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 18165 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842360.pdf [firstpage_image] =>[orig_patent_app_number] => 10452230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452230
High-density content addressable memory cell May 29, 2003 Issued
Array ( [id] => 7338198 [patent_doc_number] => 20040190350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => new [patent_app_number] => 10/447231 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6178 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20040190350.pdf [firstpage_image] =>[orig_patent_app_number] => 10447231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447231
Semiconductor memory device May 28, 2003 Issued
Array ( [id] => 6824471 [patent_doc_number] => 20030235093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/447327 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7407 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235093.pdf [firstpage_image] =>[orig_patent_app_number] => 10447327 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447327
Semiconductor memory device May 27, 2003 Issued
Array ( [id] => 1114814 [patent_doc_number] => 06804153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Semiconductor memory device internally generating internal data read timing' [patent_app_type] => B2 [patent_app_number] => 10/445934 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 24296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804153.pdf [firstpage_image] =>[orig_patent_app_number] => 10445934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445934
Semiconductor memory device internally generating internal data read timing May 27, 2003 Issued
Array ( [id] => 7627341 [patent_doc_number] => 06807100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Nonvolatile semiconductor memory device and data write method thereof' [patent_app_type] => B2 [patent_app_number] => 10/446130 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 7557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807100.pdf [firstpage_image] =>[orig_patent_app_number] => 10446130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446130
Nonvolatile semiconductor memory device and data write method thereof May 26, 2003 Issued
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