Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1191144 [patent_doc_number] => 06735135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Compact analog-multiplexed global sense amplifier for RAMs' [patent_app_type] => B2 [patent_app_number] => 10/445772 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5643 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735135.pdf [firstpage_image] =>[orig_patent_app_number] => 10445772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445772
Compact analog-multiplexed global sense amplifier for RAMs May 26, 2003 Issued
Array ( [id] => 1032604 [patent_doc_number] => 06879509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Read-only memory architecture' [patent_app_type] => utility [patent_app_number] => 10/442832 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9249 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879509.pdf [firstpage_image] =>[orig_patent_app_number] => 10442832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442832
Read-only memory architecture May 20, 2003 Issued
Array ( [id] => 1091246 [patent_doc_number] => 06829180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'High performance semiconductor memory devices' [patent_app_type] => B2 [patent_app_number] => 10/442016 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 8257 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829180.pdf [firstpage_image] =>[orig_patent_app_number] => 10442016 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442016
High performance semiconductor memory devices May 18, 2003 Issued
Array ( [id] => 7413775 [patent_doc_number] => 20040228160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Coupled body contacts for SOI differential circuits' [patent_app_type] => new [patent_app_number] => 10/436432 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3512 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20040228160.pdf [firstpage_image] =>[orig_patent_app_number] => 10436432 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436432
Coupled body contacts for SOI differential circuits May 11, 2003 Issued
Array ( [id] => 964927 [patent_doc_number] => 06950342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Differential floating gate nonvolatile memories' [patent_app_type] => utility [patent_app_number] => 10/437262 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 53 [patent_no_of_words] => 13924 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950342.pdf [firstpage_image] =>[orig_patent_app_number] => 10437262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437262
Differential floating gate nonvolatile memories May 11, 2003 Issued
Array ( [id] => 6864340 [patent_doc_number] => 20030189866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Method and apparatus for determining digital delay line entry point' [patent_app_type] => new [patent_app_number] => 10/424508 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5265 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20030189866.pdf [firstpage_image] =>[orig_patent_app_number] => 10424508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424508
Method and apparatus for determining digital delay line entry point Apr 27, 2003 Issued
Array ( [id] => 7627345 [patent_doc_number] => 06807096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 10/421628 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 40 [patent_no_of_words] => 31235 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807096.pdf [firstpage_image] =>[orig_patent_app_number] => 10421628 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421628
Nonvolatile semiconductor memory Apr 22, 2003 Issued
Array ( [id] => 6700409 [patent_doc_number] => 20030223289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Electrically erasable and programmable memory comprising an internal supply voltage management device' [patent_app_type] => new [patent_app_number] => 10/420533 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20030223289.pdf [firstpage_image] =>[orig_patent_app_number] => 10420533 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420533
Electrically erasable and programmable memory comprising an internal supply voltage management device Apr 21, 2003 Issued
Array ( [id] => 1074613 [patent_doc_number] => 06839281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Read and erase verify methods and circuits suitable for low voltage non-volatile memories' [patent_app_type] => utility [patent_app_number] => 10/414132 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5060 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839281.pdf [firstpage_image] =>[orig_patent_app_number] => 10414132 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414132
Read and erase verify methods and circuits suitable for low voltage non-volatile memories Apr 13, 2003 Issued
Array ( [id] => 7178562 [patent_doc_number] => 20040202039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Programmable delay for self-timed-margin' [patent_app_type] => new [patent_app_number] => 10/411928 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5675 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20040202039.pdf [firstpage_image] =>[orig_patent_app_number] => 10411928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411928
Programmable delay for self-timed-margin Apr 10, 2003 Issued
Array ( [id] => 1130922 [patent_doc_number] => 06791869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Nonvolatile memory device with configuration switching the number of memory cells used for one-bit data storage' [patent_app_type] => B2 [patent_app_number] => 10/410134 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 19723 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791869.pdf [firstpage_image] =>[orig_patent_app_number] => 10410134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/410134
Nonvolatile memory device with configuration switching the number of memory cells used for one-bit data storage Apr 9, 2003 Issued
Array ( [id] => 1114781 [patent_doc_number] => 06804134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Content addressable memory (CAM) devices having CAM array blocks therein that conserve bit line power during staged compare operations' [patent_app_type] => B1 [patent_app_number] => 10/410569 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 23185 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804134.pdf [firstpage_image] =>[orig_patent_app_number] => 10410569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/410569
Content addressable memory (CAM) devices having CAM array blocks therein that conserve bit line power during staged compare operations Apr 8, 2003 Issued
Array ( [id] => 1126985 [patent_doc_number] => 06795347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Memory circuit' [patent_app_type] => B2 [patent_app_number] => 10/407736 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 49 [patent_no_of_words] => 28138 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795347.pdf [firstpage_image] =>[orig_patent_app_number] => 10407736 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407736
Memory circuit Apr 3, 2003 Issued
Array ( [id] => 6820763 [patent_doc_number] => 20030218924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Method of programming memory cells by breaking down antifuse elements' [patent_app_type] => new [patent_app_number] => 10/406632 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6200 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218924.pdf [firstpage_image] =>[orig_patent_app_number] => 10406632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/406632
Method of programming memory cells by breaking down antifuse elements Apr 2, 2003 Issued
Array ( [id] => 1104511 [patent_doc_number] => 06816396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Apparatus for detecting multiple hits in a CAMRAM memory array' [patent_app_type] => B2 [patent_app_number] => 10/405736 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2271 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816396.pdf [firstpage_image] =>[orig_patent_app_number] => 10405736 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/405736
Apparatus for detecting multiple hits in a CAMRAM memory array Mar 31, 2003 Issued
Array ( [id] => 7338195 [patent_doc_number] => 20040190349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Circuit and method for decreasing the required refresh rate of DRAM devices' [patent_app_type] => new [patent_app_number] => 10/404836 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10511 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20040190349.pdf [firstpage_image] =>[orig_patent_app_number] => 10404836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/404836
Circuit and method for decreasing the required refresh rate of DRAM devices Mar 30, 2003 Issued
Array ( [id] => 1149360 [patent_doc_number] => 06778432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Thin film magnetic memory device capable of stably writing/reading data and method of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/387536 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 12745 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778432.pdf [firstpage_image] =>[orig_patent_app_number] => 10387536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/387536
Thin film magnetic memory device capable of stably writing/reading data and method of fabricating the same Mar 13, 2003 Issued
Array ( [id] => 6662347 [patent_doc_number] => 20030201673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Memory device having dual power ports and memory system including the same' [patent_app_type] => new [patent_app_number] => 10/384630 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3245 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20030201673.pdf [firstpage_image] =>[orig_patent_app_number] => 10384630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/384630
Memory device having dual power ports and memory system including the same Mar 10, 2003 Issued
Array ( [id] => 1074588 [patent_doc_number] => 06839256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same' [patent_app_type] => utility [patent_app_number] => 10/386400 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 11400 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839256.pdf [firstpage_image] =>[orig_patent_app_number] => 10386400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/386400
Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same Mar 10, 2003 Issued
Array ( [id] => 1163746 [patent_doc_number] => 06765827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method and system for detecting defective material surrounding flash memory cells' [patent_app_type] => B1 [patent_app_number] => 10/384936 [patent_app_country] => US [patent_app_date] => 2003-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4186 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765827.pdf [firstpage_image] =>[orig_patent_app_number] => 10384936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/384936
Method and system for detecting defective material surrounding flash memory cells Mar 9, 2003 Issued
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