Dirk Wright

Array ( [id] => 6795683 [patent_doc_number] => 20030174556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Method and device for verifying a group of non-volatile memory cells' [patent_app_type] => new [patent_app_number] => 10/363234 [patent_app_country] => US [patent_app_date] => 2003-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2094 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20030174556.pdf [firstpage_image] =>[orig_patent_app_number] => 10363234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7398374 [patent_doc_number] => 20040174758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Memory device with high charging voltage bit line' [patent_app_type] => new [patent_app_number] => 10/378231 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2364 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174758.pdf [firstpage_image] =>[orig_patent_app_number] => 10378231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1156138 [patent_doc_number] => 06775195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Apparatus and method for accessing a magnetoresistive random access memory array' [patent_app_type] => B1 [patent_app_number] => 10/377530 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5544 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775195.pdf [firstpage_image] =>[orig_patent_app_number] => 10377530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6855108 [patent_doc_number] => 20030128609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'DRAM with bias sensing' [patent_app_type] => new [patent_app_number] => 10/375626 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2193 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128609.pdf [firstpage_image] =>[orig_patent_app_number] => 10375626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6709864 [patent_doc_number] => 20030169613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Signal detection circuit for detecting multiple match in arranged signal lines' [patent_app_type] => new [patent_app_number] => 10/372230 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4935 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20030169613.pdf [firstpage_image] =>[orig_patent_app_number] => 10372230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183224 [patent_doc_number] => 06744676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same' [patent_app_type] => B2 [patent_app_number] => 10/374956 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 64 [patent_no_of_words] => 18580 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744676.pdf [firstpage_image] =>[orig_patent_app_number] => 10374956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1048486 [patent_doc_number] => 06865114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Word line selector for a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/372626 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6870 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/865/06865114.pdf [firstpage_image] =>[orig_patent_app_number] => 10372626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6827958 [patent_doc_number] => 20030179016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Serial data detection circuit performing same offset adjustment to signal receiver as performed to reference receiver' [patent_app_type] => new [patent_app_number] => 10/368878 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7105 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20030179016.pdf [firstpage_image] =>[orig_patent_app_number] => 10368878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183184 [patent_doc_number] => 06744665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Memory cell configuration' [patent_app_type] => B2 [patent_app_number] => 10/368331 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744665.pdf [firstpage_image] =>[orig_patent_app_number] => 10368331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6739114 [patent_doc_number] => 20030156483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Integrated dynamic memory with control circuit for controlling a refresh mode of memory cells, and method for driving the memory' [patent_app_type] => new [patent_app_number] => 10/368333 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2913 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20030156483.pdf [firstpage_image] =>[orig_patent_app_number] => 10368333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6739077 [patent_doc_number] => 20030156446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Integrated memory circuit having storage capacitors which can be written to via word lines and bit lines' [patent_app_type] => new [patent_app_number] => 10/368332 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20030156446.pdf [firstpage_image] =>[orig_patent_app_number] => 10368332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1104558 [patent_doc_number] => 06816415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'ADDITIONAL INFORMATION READ/WRITE SYSTEM, ADDITIONAL INFORMATION READ/WRITE METHOD, ADDITIONAL INFORMATION READ/WRITE PROGRAM, COMPUTER-READABLE PROGRAM STORAGE MEDIUM STORING ADDITIONAL INFORMATION READ/WRITE PROGRAM, AND ID/ADDITIONAL INFORMATION DISTRIBUTING APPARATUS.' [patent_app_type] => B2 [patent_app_number] => 10/361829 [patent_app_country] => US [patent_app_date] => 2003-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4805 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816415.pdf [firstpage_image] =>[orig_patent_app_number] => 10361829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6855113 [patent_doc_number] => 20030128614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING REFRESH SIZE SETTING CIRCUIT' [patent_app_type] => new [patent_app_number] => 10/359058 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 35223 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128614.pdf [firstpage_image] =>[orig_patent_app_number] => 10359058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7131892 [patent_doc_number] => 20040042310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Refresh type semiconductor memory device having refresh circuit for minimizing refresh fail at high speed operation' [patent_app_type] => new [patent_app_number] => 10/359531 [patent_app_country] => US [patent_app_date] => 2003-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4577 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042310.pdf [firstpage_image] =>[orig_patent_app_number] => 10359531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7614427 [patent_doc_number] => 06898103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Memory cell with fuse element' [patent_app_type] => utility [patent_app_number] => 10/352417 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898103.pdf [firstpage_image] =>[orig_patent_app_number] => 10352417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7162903 [patent_doc_number] => 20040076037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Flash memory architecture with page mode erase using NMOS and PMOS row decoding scheme' [patent_app_type] => new [patent_app_number] => 10/352734 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6003 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20040076037.pdf [firstpage_image] =>[orig_patent_app_number] => 10352734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6667674 [patent_doc_number] => 20030112657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Magneto-resistive memory array' [patent_app_type] => new [patent_app_number] => 10/352278 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10253 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112657.pdf [firstpage_image] =>[orig_patent_app_number] => 10352278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7626090 [patent_doc_number] => 06768676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/350332 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 12172 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768676.pdf [firstpage_image] =>[orig_patent_app_number] => 10350332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1135694 [patent_doc_number] => 06788589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Programmable latch circuit inserted into write data path of an integrated circuit memory' [patent_app_type] => B2 [patent_app_number] => 10/349334 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2800 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788589.pdf [firstpage_image] =>[orig_patent_app_number] => 10349334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7434003 [patent_doc_number] => 20040008564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Memory device for activating one cell by specifying block and memory cell in the block' [patent_app_type] => new [patent_app_number] => 10/347434 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5609 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20040008564.pdf [firstpage_image] =>[orig_patent_app_number] => 10347434 [rel_patent_id] =>[rel_patent_doc_number] =>)