Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6657340 [patent_doc_number] => 20030133321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Random access memory and method for controlling operations of reading, writing, and refreshing data of the same' [patent_app_type] => new [patent_app_number] => 10/273947 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4143 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20030133321.pdf [firstpage_image] =>[orig_patent_app_number] => 10273947 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273947
Random access memory and method for controlling operations of reading, writing, and refreshing data of the same Oct 17, 2002 Issued
Array ( [id] => 6719668 [patent_doc_number] => 20030053356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Non-volatile memory and method of non-volatile memory programming' [patent_app_type] => new [patent_app_number] => 10/270057 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14542 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053356.pdf [firstpage_image] =>[orig_patent_app_number] => 10270057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270057
Non-volatile memory and method of non-volatile memory programming Oct 14, 2002 Issued
Array ( [id] => 883113 [patent_doc_number] => 07355912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Auto-precharge control circuit in semiconductor memory and method thereof' [patent_app_type] => utility [patent_app_number] => 10/268732 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5737 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355912.pdf [firstpage_image] =>[orig_patent_app_number] => 10268732 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268732
Auto-precharge control circuit in semiconductor memory and method thereof Oct 10, 2002 Issued
Array ( [id] => 1172797 [patent_doc_number] => 06760260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => B2 [patent_app_number] => 10/269834 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2343 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760260.pdf [firstpage_image] =>[orig_patent_app_number] => 10269834 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269834
Semiconductor memory apparatus Oct 10, 2002 Issued
Array ( [id] => 7279740 [patent_doc_number] => 20040062117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having diode isolation' [patent_app_type] => new [patent_app_number] => 10/261532 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8087 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20040062117.pdf [firstpage_image] =>[orig_patent_app_number] => 10261532 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261532
Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having diode isolation Sep 30, 2002 Issued
Array ( [id] => 1048490 [patent_doc_number] => 06865115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Input stage apparatus and method having a variable reference voltage' [patent_app_type] => utility [patent_app_number] => 10/256037 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 0 [patent_no_of_words] => 4225 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/865/06865115.pdf [firstpage_image] =>[orig_patent_app_number] => 10256037 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256037
Input stage apparatus and method having a variable reference voltage Sep 24, 2002 Issued
Array ( [id] => 6673117 [patent_doc_number] => 20030058720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Semiconductor memory device with stable precharge voltage level of data lines' [patent_app_type] => new [patent_app_number] => 10/252530 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3230 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058720.pdf [firstpage_image] =>[orig_patent_app_number] => 10252530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252530
Semiconductor memory device with stable precharge voltage level of data lines Sep 23, 2002 Issued
Array ( [id] => 7268769 [patent_doc_number] => 20040057287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Non-volatile memory and method with reduced source line bias errors' [patent_app_type] => new [patent_app_number] => 10/254830 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14199 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20040057287.pdf [firstpage_image] =>[orig_patent_app_number] => 10254830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254830
Non-volatile memory and method with reduced source line bias errors Sep 23, 2002 Issued
Array ( [id] => 6719666 [patent_doc_number] => 20030053354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Method for operating a semiconductor memory and semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/247572 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3871 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053354.pdf [firstpage_image] =>[orig_patent_app_number] => 10247572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247572
Method for operating a semiconductor memory and semiconductor memory Sep 18, 2002 Issued
Array ( [id] => 7632124 [patent_doc_number] => 06665212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Reference current generating circuit of multiple bit flash memory' [patent_app_type] => B1 [patent_app_number] => 10/065032 [patent_app_country] => US [patent_app_date] => 2002-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2746 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665212.pdf [firstpage_image] =>[orig_patent_app_number] => 10065032 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065032
Reference current generating circuit of multiple bit flash memory Sep 11, 2002 Issued
Array ( [id] => 1122894 [patent_doc_number] => 06798707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Memory control apparatus for serial memory' [patent_app_type] => B2 [patent_app_number] => 10/234132 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6894 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798707.pdf [firstpage_image] =>[orig_patent_app_number] => 10234132 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/234132
Memory control apparatus for serial memory Sep 4, 2002 Issued
Array ( [id] => 1216081 [patent_doc_number] => 06711051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Static RAM architecture with bit line partitioning' [patent_app_type] => B1 [patent_app_number] => 10/235530 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 4837 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711051.pdf [firstpage_image] =>[orig_patent_app_number] => 10235530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/235530
Static RAM architecture with bit line partitioning Sep 4, 2002 Issued
Array ( [id] => 7623005 [patent_doc_number] => 06687160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Reference current generation circuit for multiple bit flash memory' [patent_app_type] => B1 [patent_app_number] => 10/064918 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2751 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687160.pdf [firstpage_image] =>[orig_patent_app_number] => 10064918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064918
Reference current generation circuit for multiple bit flash memory Aug 28, 2002 Issued
Array ( [id] => 1288198 [patent_doc_number] => 06643176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Reference current generation circuit for multiple bit flash memory' [patent_app_type] => B1 [patent_app_number] => 10/064917 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2856 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643176.pdf [firstpage_image] =>[orig_patent_app_number] => 10064917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064917
Reference current generation circuit for multiple bit flash memory Aug 28, 2002 Issued
Array ( [id] => 1023583 [patent_doc_number] => 06888742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Off-axis pinned layer magnetic element utilizing spin transfer and an MRAM device using the magnetic element' [patent_app_type] => utility [patent_app_number] => 10/231430 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12086 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888742.pdf [firstpage_image] =>[orig_patent_app_number] => 10231430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231430
Off-axis pinned layer magnetic element utilizing spin transfer and an MRAM device using the magnetic element Aug 27, 2002 Issued
Array ( [id] => 6754602 [patent_doc_number] => 20030002378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Semiconductor memory device and information processing system' [patent_app_type] => new [patent_app_number] => 10/227430 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13768 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002378.pdf [firstpage_image] =>[orig_patent_app_number] => 10227430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227430
Semiconductor memory device and information processing system Aug 25, 2002 Issued
Array ( [id] => 1204630 [patent_doc_number] => 06721224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'Memory refresh methods and circuits' [patent_app_type] => B2 [patent_app_number] => 10/228530 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5454 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721224.pdf [firstpage_image] =>[orig_patent_app_number] => 10228530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228530
Memory refresh methods and circuits Aug 25, 2002 Issued
Array ( [id] => 7386120 [patent_doc_number] => 20040037114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Preconditioning global bitlines' [patent_app_type] => new [patent_app_number] => 10/227734 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3026 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037114.pdf [firstpage_image] =>[orig_patent_app_number] => 10227734 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227734
Preconditioning global bitlines Aug 25, 2002 Issued
Array ( [id] => 7386124 [patent_doc_number] => 20040037115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'FLASH MEMORY DEVICE WITH DISTRIBUTED COUPLING BETWEEN ARRAY GROUND AND SUBSTRATE' [patent_app_type] => new [patent_app_number] => 10/225130 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5753 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037115.pdf [firstpage_image] =>[orig_patent_app_number] => 10225130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225130
Flash memory device with distributed coupling between array ground and substrate Aug 21, 2002 Issued
Array ( [id] => 6764740 [patent_doc_number] => 20030099138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Devices and methods for controlling active termination resistors in a memory system' [patent_app_type] => new [patent_app_number] => 10/224632 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6675 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20030099138.pdf [firstpage_image] =>[orig_patent_app_number] => 10224632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224632
Devices and methods for controlling active termination resistors in a memory system Aug 20, 2002 Issued
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