Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1280672 [patent_doc_number] => 06650572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Compact analog-multiplexed global sense amplifier for rams' [patent_app_type] => B2 [patent_app_number] => 10/224841 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5596 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/650/06650572.pdf [firstpage_image] =>[orig_patent_app_number] => 10224841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224841
Compact analog-multiplexed global sense amplifier for rams Aug 20, 2002 Issued
Array ( [id] => 6691723 [patent_doc_number] => 20030039155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Integrated memory with memory cells in a plurality of memory cell blocks, and method of operating such a memory' [patent_app_type] => new [patent_app_number] => 10/217936 [patent_app_country] => US [patent_app_date] => 2002-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3390 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20030039155.pdf [firstpage_image] =>[orig_patent_app_number] => 10217936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/217936
Integrated memory with memory cells in a plurality of memory cell blocks, and method of operating such a memory Aug 12, 2002 Issued
Array ( [id] => 6687322 [patent_doc_number] => 20030031045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Magnetic random access memory including memory cell unit and reference cell unit' [patent_app_type] => new [patent_app_number] => 10/212734 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7218 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20030031045.pdf [firstpage_image] =>[orig_patent_app_number] => 10212734 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212734
Magnetic random access memory including memory cell unit and reference cell unit Aug 6, 2002 Issued
Array ( [id] => 7391451 [patent_doc_number] => 20040022085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Refreshing memory cells of a phase change material memory device' [patent_app_type] => new [patent_app_number] => 10/212630 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10195 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20040022085.pdf [firstpage_image] =>[orig_patent_app_number] => 10212630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212630
Refreshing memory cells of a phase change material memory device Aug 4, 2002 Issued
Array ( [id] => 1334766 [patent_doc_number] => 06600691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'High frequency range four bit prefetch output data path' [patent_app_type] => B2 [patent_app_number] => 10/207641 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 10053 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600691.pdf [firstpage_image] =>[orig_patent_app_number] => 10207641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/207641
High frequency range four bit prefetch output data path Jul 28, 2002 Issued
Array ( [id] => 6850370 [patent_doc_number] => 20030142572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Semiconductor device capable of reliable power-on reset' [patent_app_type] => new [patent_app_number] => 10/205435 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7645 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20030142572.pdf [firstpage_image] =>[orig_patent_app_number] => 10205435 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205435
Semiconductor device capable of reliable power-on reset Jul 25, 2002 Issued
Array ( [id] => 6695744 [patent_doc_number] => 20030107938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Apparatus for controlling refresh of memory device without external refresh command and method thereof' [patent_app_type] => new [patent_app_number] => 10/205334 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2158 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107938.pdf [firstpage_image] =>[orig_patent_app_number] => 10205334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205334
Apparatus for controlling refresh of memory device without external refresh command and method thereof Jul 24, 2002 Issued
Array ( [id] => 1163662 [patent_doc_number] => 06765819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Magnetic memory device having improved switching characteristics' [patent_app_type] => B1 [patent_app_number] => 10/205531 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4588 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765819.pdf [firstpage_image] =>[orig_patent_app_number] => 10205531 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205531
Magnetic memory device having improved switching characteristics Jul 24, 2002 Issued
Array ( [id] => 6749126 [patent_doc_number] => 20030043646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Semiconductor memory device with detection circuit' [patent_app_type] => new [patent_app_number] => 10/201137 [patent_app_country] => US [patent_app_date] => 2002-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13270 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20030043646.pdf [firstpage_image] =>[orig_patent_app_number] => 10201137 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/201137
Semiconductor memory device with detection circuit Jul 23, 2002 Issued
Array ( [id] => 7632122 [patent_doc_number] => 06665214 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode' [patent_app_type] => B1 [patent_app_number] => 10/200330 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 83 [patent_no_of_words] => 62106 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665214.pdf [firstpage_image] =>[orig_patent_app_number] => 10200330 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/200330
On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode Jul 21, 2002 Issued
Array ( [id] => 1268904 [patent_doc_number] => 06661706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Semiconductor storage device having page copying' [patent_app_type] => B2 [patent_app_number] => 10/194337 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4763 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661706.pdf [firstpage_image] =>[orig_patent_app_number] => 10194337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/194337
Semiconductor storage device having page copying Jul 11, 2002 Issued
Array ( [id] => 6777592 [patent_doc_number] => 20030048673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Test mode decoder in a flash memory' [patent_app_type] => new [patent_app_number] => 10/192334 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10280 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20030048673.pdf [firstpage_image] =>[orig_patent_app_number] => 10192334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192334
Test mode decoder in a flash memory Jul 9, 2002 Issued
Array ( [id] => 1191097 [patent_doc_number] => 06735108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'ROM embedded DRAM with anti-fuse programming' [patent_app_type] => B2 [patent_app_number] => 10/190631 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735108.pdf [firstpage_image] =>[orig_patent_app_number] => 10190631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190631
ROM embedded DRAM with anti-fuse programming Jul 7, 2002 Issued
Array ( [id] => 6687325 [patent_doc_number] => 20030031048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Bit line decoding scheme and circuit for dual bit memory with a dual bit selection' [patent_app_type] => new [patent_app_number] => 10/190633 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20030031048.pdf [firstpage_image] =>[orig_patent_app_number] => 10190633 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190633
Bit line decoding scheme and circuit for dual bit memory with a dual bit selection Jul 7, 2002 Issued
Array ( [id] => 1295776 [patent_doc_number] => 06631088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-07 [patent_title] => 'Twin MONOS array metal bit organization and single cell operation' [patent_app_type] => B2 [patent_app_number] => 10/190634 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3133 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631088.pdf [firstpage_image] =>[orig_patent_app_number] => 10190634 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190634
Twin MONOS array metal bit organization and single cell operation Jul 7, 2002 Issued
Array ( [id] => 7630498 [patent_doc_number] => 06636438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Control gate decoder for twin MONOS memory with two bit erase capability' [patent_app_type] => B2 [patent_app_number] => 10/190635 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5132 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636438.pdf [firstpage_image] =>[orig_patent_app_number] => 10190635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190635
Control gate decoder for twin MONOS memory with two bit erase capability Jul 7, 2002 Issued
Array ( [id] => 1295784 [patent_doc_number] => 06631089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Bit line decoding scheme and circuit for dual bit memory array' [patent_app_type] => B1 [patent_app_number] => 10/190636 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6882 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631089.pdf [firstpage_image] =>[orig_patent_app_number] => 10190636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190636
Bit line decoding scheme and circuit for dual bit memory array Jul 7, 2002 Issued
Array ( [id] => 7360260 [patent_doc_number] => 20040004861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Differential EEPROM using pFET floating gate transistors' [patent_app_type] => new [patent_app_number] => 10/190337 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8493 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004861.pdf [firstpage_image] =>[orig_patent_app_number] => 10190337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190337
Differential EEPROM using pFET floating gate transistors Jul 4, 2002 Abandoned
Array ( [id] => 1199330 [patent_doc_number] => 06728146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Memory device and method for automatically repairing defective memory cells' [patent_app_type] => B1 [patent_app_number] => 10/189134 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728146.pdf [firstpage_image] =>[orig_patent_app_number] => 10189134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/189134
Memory device and method for automatically repairing defective memory cells Jul 2, 2002 Issued
Array ( [id] => 776043 [patent_doc_number] => 07002859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'On-die switchable test circuit' [patent_app_type] => utility [patent_app_number] => 10/187726 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1972 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002859.pdf [firstpage_image] =>[orig_patent_app_number] => 10187726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/187726
On-die switchable test circuit Jul 1, 2002 Issued
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