Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1426273 [patent_doc_number] => 06510095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Semiconductor memory device for operating in synchronization with edge of clock signal' [patent_app_type] => B1 [patent_app_number] => 10/073231 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12457 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510095.pdf [firstpage_image] =>[orig_patent_app_number] => 10073231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073231
Semiconductor memory device for operating in synchronization with edge of clock signal Feb 12, 2002 Issued
Array ( [id] => 6046041 [patent_doc_number] => 20020167841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Boost device for nonvolatile memories with an integrated stand-by charge pump' [patent_app_type] => new [patent_app_number] => 10/076134 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3494 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167841.pdf [firstpage_image] =>[orig_patent_app_number] => 10076134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076134
Boost device for nonvolatile memories with an integrated stand-by charge pump Feb 12, 2002 Issued
Array ( [id] => 1426103 [patent_doc_number] => 06510076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Variable read/write margin high-performance soft-error tolerant SRAM bit cell' [patent_app_type] => B1 [patent_app_number] => 10/073036 [patent_app_country] => US [patent_app_date] => 2002-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5704 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510076.pdf [firstpage_image] =>[orig_patent_app_number] => 10073036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073036
Variable read/write margin high-performance soft-error tolerant SRAM bit cell Feb 11, 2002 Issued
Array ( [id] => 6644173 [patent_doc_number] => 20030007403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'SEMICONDUCTOR MEMORY HAVING A WIDE BUS-BANDWIDTH FOR INPUT/OUTPUT DATA' [patent_app_type] => new [patent_app_number] => 10/067236 [patent_app_country] => US [patent_app_date] => 2002-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8951 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007403.pdf [firstpage_image] =>[orig_patent_app_number] => 10067236 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/067236
Semiconductor memory having a wide bus-bandwidth for input/output data Feb 6, 2002 Issued
Array ( [id] => 6207268 [patent_doc_number] => 20020071329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'DRAM core refresh with reduced spike current' [patent_app_type] => new [patent_app_number] => 10/066042 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20020071329.pdf [firstpage_image] =>[orig_patent_app_number] => 10066042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066042
DRAM core refresh with reduced spike current Jan 28, 2002 Issued
Array ( [id] => 1507453 [patent_doc_number] => 06466509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Semiconductor memory device having a column select line transmitting a column select signal' [patent_app_type] => B1 [patent_app_number] => 10/050131 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 36 [patent_no_of_words] => 15068 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466509.pdf [firstpage_image] =>[orig_patent_app_number] => 10050131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050131
Semiconductor memory device having a column select line transmitting a column select signal Jan 17, 2002 Issued
Array ( [id] => 1342189 [patent_doc_number] => 06597622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter' [patent_app_type] => B2 [patent_app_number] => 10/046174 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3047 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597622.pdf [firstpage_image] =>[orig_patent_app_number] => 10046174 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/046174
Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter Jan 15, 2002 Issued
Array ( [id] => 1429556 [patent_doc_number] => 06515929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Partial refresh feature in pseudo SRAM' [patent_app_type] => B1 [patent_app_number] => 10/050433 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515929.pdf [firstpage_image] =>[orig_patent_app_number] => 10050433 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050433
Partial refresh feature in pseudo SRAM Jan 15, 2002 Issued
Array ( [id] => 1376628 [patent_doc_number] => 06570782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Storage and retrieval for resistance-based memory devices' [patent_app_type] => B1 [patent_app_number] => 10/050668 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5915 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570782.pdf [firstpage_image] =>[orig_patent_app_number] => 10050668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050668
Storage and retrieval for resistance-based memory devices Jan 15, 2002 Issued
Array ( [id] => 1401707 [patent_doc_number] => 06552921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory' [patent_app_type] => B2 [patent_app_number] => 10/050075 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3334 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552921.pdf [firstpage_image] =>[orig_patent_app_number] => 10050075 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050075
Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory Jan 14, 2002 Issued
Array ( [id] => 1413496 [patent_doc_number] => 06542401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'SRAM device' [patent_app_type] => B2 [patent_app_number] => 10/043134 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6485 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542401.pdf [firstpage_image] =>[orig_patent_app_number] => 10043134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043134
SRAM device Jan 13, 2002 Issued
Array ( [id] => 6014072 [patent_doc_number] => 20020101776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Operation method of a SRAM device' [patent_app_type] => new [patent_app_number] => 10/047765 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4503 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20020101776.pdf [firstpage_image] =>[orig_patent_app_number] => 10047765 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/047765
Operation method of a SRAM device Jan 13, 2002 Issued
Array ( [id] => 1275848 [patent_doc_number] => 06654295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Reduced topography DRAM cell fabricated using a modified logic process and method for operating same' [patent_app_type] => B2 [patent_app_number] => 10/043386 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 52 [patent_no_of_words] => 16250 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654295.pdf [firstpage_image] =>[orig_patent_app_number] => 10043386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043386
Reduced topography DRAM cell fabricated using a modified logic process and method for operating same Jan 10, 2002 Issued
Array ( [id] => 6455333 [patent_doc_number] => 20020149990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Semiconductor memory device having asymmetric data paths' [patent_app_type] => new [patent_app_number] => 10/044770 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2976 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149990.pdf [firstpage_image] =>[orig_patent_app_number] => 10044770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044770
Semiconductor memory device having asymmetric data paths Jan 9, 2002 Issued
Array ( [id] => 1350062 [patent_doc_number] => 06590809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/040332 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 4203 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590809.pdf [firstpage_image] =>[orig_patent_app_number] => 10040332 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040332
Non-volatile semiconductor memory device Jan 8, 2002 Issued
Array ( [id] => 6520240 [patent_doc_number] => 20020136079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Semiconductor memory device and information processing system' [patent_app_type] => new [patent_app_number] => 10/036470 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11082 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136079.pdf [firstpage_image] =>[orig_patent_app_number] => 10036470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036470
Semiconductor memory device and information processing system Jan 6, 2002 Abandoned
Array ( [id] => 1429532 [patent_doc_number] => 06515926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time' [patent_app_type] => B1 [patent_app_number] => 10/038932 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4070 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515926.pdf [firstpage_image] =>[orig_patent_app_number] => 10038932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038932
Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time Jan 3, 2002 Issued
Array ( [id] => 1423530 [patent_doc_number] => 06529405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Circuit and method for programming and reading multi-level flash memory' [patent_app_type] => B2 [patent_app_number] => 10/029034 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4147 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529405.pdf [firstpage_image] =>[orig_patent_app_number] => 10029034 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029034
Circuit and method for programming and reading multi-level flash memory Dec 27, 2001 Issued
Array ( [id] => 1423670 [patent_doc_number] => 06529419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Apparatus for varying data input/output path in semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/028431 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2634 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529419.pdf [firstpage_image] =>[orig_patent_app_number] => 10028431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028431
Apparatus for varying data input/output path in semiconductor memory device Dec 27, 2001 Issued
Array ( [id] => 6126520 [patent_doc_number] => 20020075728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Compressed event counting technique and application to a flash memory system' [patent_app_type] => new [patent_app_number] => 10/033222 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10410 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075728.pdf [firstpage_image] =>[orig_patent_app_number] => 10033222 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033222
Compressed event counting technique and application to a flash memory system Dec 26, 2001 Issued
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