Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6682007 [patent_doc_number] => 20030117871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'MEMORY MODULE WITH TEST MODE' [patent_app_type] => new [patent_app_number] => 10/036772 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2764 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117871.pdf [firstpage_image] =>[orig_patent_app_number] => 10036772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036772
Memory module with test mode Dec 20, 2001 Issued
Array ( [id] => 7623007 [patent_doc_number] => 06687158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Gapless programming for a NAND type flash memory' [patent_app_type] => B2 [patent_app_number] => 10/029666 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5439 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687158.pdf [firstpage_image] =>[orig_patent_app_number] => 10029666 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029666
Gapless programming for a NAND type flash memory Dec 20, 2001 Issued
Array ( [id] => 6604667 [patent_doc_number] => 20020064066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/024008 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7553 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064066.pdf [firstpage_image] =>[orig_patent_app_number] => 10024008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/024008
Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device Dec 20, 2001 Issued
Array ( [id] => 1275916 [patent_doc_number] => 06654309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Circuit and method for reducing voltage stress in a memory decoder' [patent_app_type] => B1 [patent_app_number] => 10/029371 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3833 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654309.pdf [firstpage_image] =>[orig_patent_app_number] => 10029371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029371
Circuit and method for reducing voltage stress in a memory decoder Dec 19, 2001 Issued
Array ( [id] => 1425622 [patent_doc_number] => 06525955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Memory cell with fuse element' [patent_app_type] => B1 [patent_app_number] => 10/025132 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4132 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525955.pdf [firstpage_image] =>[orig_patent_app_number] => 10025132 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/025132
Memory cell with fuse element Dec 17, 2001 Issued
Array ( [id] => 6435579 [patent_doc_number] => 20020176287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Redundancy circuit of semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/020168 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 19184 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20020176287.pdf [firstpage_image] =>[orig_patent_app_number] => 10020168 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020168
Redundancy circuit of semiconductor memory device Dec 17, 2001 Issued
Array ( [id] => 1389983 [patent_doc_number] => 06563745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Memory device and method for dynamic bit inversion' [patent_app_type] => B1 [patent_app_number] => 10/023466 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5468 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563745.pdf [firstpage_image] =>[orig_patent_app_number] => 10023466 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023466
Memory device and method for dynamic bit inversion Dec 13, 2001 Issued
Array ( [id] => 1427084 [patent_doc_number] => 06522570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'System and method for inhibiting imprinting of capacitor structures of a memory' [patent_app_type] => B1 [patent_app_number] => 10/022036 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4082 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522570.pdf [firstpage_image] =>[orig_patent_app_number] => 10022036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/022036
System and method for inhibiting imprinting of capacitor structures of a memory Dec 12, 2001 Issued
Array ( [id] => 1425808 [patent_doc_number] => 06525973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Automatic bitline-latch loading for flash prom test' [patent_app_type] => B1 [patent_app_number] => 10/020536 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5759 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525973.pdf [firstpage_image] =>[orig_patent_app_number] => 10020536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020536
Automatic bitline-latch loading for flash prom test Dec 11, 2001 Issued
Array ( [id] => 6695741 [patent_doc_number] => 20030107935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'DRAM WITH BIAS SENSING' [patent_app_type] => new [patent_app_number] => 10/017868 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2153 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107935.pdf [firstpage_image] =>[orig_patent_app_number] => 10017868 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017868
DRAM with bias sensing Dec 11, 2001 Issued
Array ( [id] => 1406871 [patent_doc_number] => 06549460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Memory device and memory card' [patent_app_type] => B2 [patent_app_number] => 10/012525 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6969 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549460.pdf [firstpage_image] =>[orig_patent_app_number] => 10012525 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/012525
Memory device and memory card Dec 11, 2001 Issued
Array ( [id] => 1454409 [patent_doc_number] => 06456545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for data transmission and reception' [patent_app_type] => B1 [patent_app_number] => 10/010230 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456545.pdf [firstpage_image] =>[orig_patent_app_number] => 10010230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010230
Method and apparatus for data transmission and reception Dec 6, 2001 Issued
Array ( [id] => 1428363 [patent_doc_number] => 06507529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/003430 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10186 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507529.pdf [firstpage_image] =>[orig_patent_app_number] => 10003430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003430
Semiconductor device Dec 5, 2001 Issued
Array ( [id] => 5827182 [patent_doc_number] => 20020067641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Usage of word voltage assistance in twin MONOS cell during program and erase' [patent_app_type] => new [patent_app_number] => 10/005932 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3938 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067641.pdf [firstpage_image] =>[orig_patent_app_number] => 10005932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005932
Usage of word voltage assistance in twin MONOS cell during program and erase Dec 4, 2001 Issued
Array ( [id] => 1425310 [patent_doc_number] => 06512710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Reliability test method and circuit for non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 10/004636 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2510 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512710.pdf [firstpage_image] =>[orig_patent_app_number] => 10004636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004636
Reliability test method and circuit for non-volatile memory Dec 3, 2001 Issued
Array ( [id] => 1572658 [patent_doc_number] => 06498746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Disturbing a ferroelectric memory array in a particular direction' [patent_app_type] => B1 [patent_app_number] => 10/004972 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3700 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498746.pdf [firstpage_image] =>[orig_patent_app_number] => 10004972 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004972
Disturbing a ferroelectric memory array in a particular direction Dec 2, 2001 Issued
Array ( [id] => 5966256 [patent_doc_number] => 20020089871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Ferroelectric memory devices with memory cells in a row connected to different plate lines' [patent_app_type] => new [patent_app_number] => 10/005445 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6301 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20020089871.pdf [firstpage_image] =>[orig_patent_app_number] => 10005445 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005445
Ferroelectric memory devices with memory cells in a row connected to different plate lines Dec 2, 2001 Issued
Array ( [id] => 1523345 [patent_doc_number] => 06414879 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/996616 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6208 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414879.pdf [firstpage_image] =>[orig_patent_app_number] => 09996616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996616
Semiconductor memory device Nov 29, 2001 Issued
Array ( [id] => 7644624 [patent_doc_number] => 06473349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Cascode sense AMP and column select circuit and method of operation' [patent_app_type] => B1 [patent_app_number] => 09/997330 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4876 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473349.pdf [firstpage_image] =>[orig_patent_app_number] => 09997330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997330
Cascode sense AMP and column select circuit and method of operation Nov 28, 2001 Issued
Array ( [id] => 6207266 [patent_doc_number] => 20020071327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Memory device with reduced refresh noise' [patent_app_type] => new [patent_app_number] => 09/993770 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2327 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20020071327.pdf [firstpage_image] =>[orig_patent_app_number] => 09993770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/993770
Memory device with reduced refresh noise Nov 26, 2001 Issued
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