
Dirk Wright
Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )
| Most Active Art Unit | 3502 |
| Art Unit(s) | 3502, 3656, 3659, 3622, 3655, 2899, 3681 |
| Total Applications | 4396 |
| Issued Applications | 4127 |
| Pending Applications | 57 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6435746
[patent_doc_number] => 20020176300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Refresh-circuit-containing semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 09/988172
[patent_app_country] => US
[patent_app_date] => 2001-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5418
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20020176300.pdf
[firstpage_image] =>[orig_patent_app_number] => 09988172
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/988172 | Refresh-circuit-containing semiconductor memory device | Nov 18, 2001 | Issued |
Array
(
[id] => 6800292
[patent_doc_number] => 20030095456
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'SENSE AMPLIFIER WITH INDEPENDENT WRITE-BACK CAPABILITY FOR FERROELECTRIC RANDOM-ACCESS MEMORIES'
[patent_app_type] => new
[patent_app_number] => 09/991571
[patent_app_country] => US
[patent_app_date] => 2001-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1337
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20030095456.pdf
[firstpage_image] =>[orig_patent_app_number] => 09991571
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/991571 | Sense amplifier with independent write-back capability for ferroelectric random-access memories | Nov 15, 2001 | Issued |
Array
(
[id] => 1431748
[patent_doc_number] => 06504787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-07
[patent_title] => 'Semiconductor memory device with reduced power consumption during refresh operation'
[patent_app_type] => B2
[patent_app_number] => 09/987836
[patent_app_country] => US
[patent_app_date] => 2001-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 8424
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/504/06504787.pdf
[firstpage_image] =>[orig_patent_app_number] => 09987836
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/987836 | Semiconductor memory device with reduced power consumption during refresh operation | Nov 15, 2001 | Issued |
Array
(
[id] => 1425378
[patent_doc_number] => 06512715
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-28
[patent_title] => 'Semiconductor memory device operating with low power consumption'
[patent_app_type] => B2
[patent_app_number] => 09/987837
[patent_app_country] => US
[patent_app_date] => 2001-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 19596
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/512/06512715.pdf
[firstpage_image] =>[orig_patent_app_number] => 09987837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/987837 | Semiconductor memory device operating with low power consumption | Nov 15, 2001 | Issued |
Array
(
[id] => 6338045
[patent_doc_number] => 20020034095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-21
[patent_title] => 'Magneto-resistive memory array'
[patent_app_type] => new
[patent_app_number] => 09/992213
[patent_app_country] => US
[patent_app_date] => 2001-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10212
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20020034095.pdf
[firstpage_image] =>[orig_patent_app_number] => 09992213
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/992213 | Magneto-resistive memory array | Nov 13, 2001 | Issued |
Array
(
[id] => 1425181
[patent_doc_number] => 06512696
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-28
[patent_title] => 'Method of programming and erasing a SNNNS type non-volatile memory cell'
[patent_app_type] => B1
[patent_app_number] => 09/986932
[patent_app_country] => US
[patent_app_date] => 2001-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2155
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/512/06512696.pdf
[firstpage_image] =>[orig_patent_app_number] => 09986932
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/986932 | Method of programming and erasing a SNNNS type non-volatile memory cell | Nov 12, 2001 | Issued |
Array
(
[id] => 6435692
[patent_doc_number] => 20020176295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE ALLOWING EASY CHARACTERISTICS EVALUATION'
[patent_app_type] => new
[patent_app_number] => 09/986874
[patent_app_country] => US
[patent_app_date] => 2001-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6273
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20020176295.pdf
[firstpage_image] =>[orig_patent_app_number] => 09986874
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/986874 | Semiconductor memory device allowing easy characteristics evaluation | Nov 12, 2001 | Issued |
Array
(
[id] => 1419112
[patent_doc_number] => 06535449
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-18
[patent_title] => 'Semiconductor memory unit in which power consumption can be restricted'
[patent_app_type] => B2
[patent_app_number] => 09/986873
[patent_app_country] => US
[patent_app_date] => 2001-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 1663
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/535/06535449.pdf
[firstpage_image] =>[orig_patent_app_number] => 09986873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/986873 | Semiconductor memory unit in which power consumption can be restricted | Nov 12, 2001 | Issued |
Array
(
[id] => 1427124
[patent_doc_number] => 06522575
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-18
[patent_title] => 'Semiconductor memory device having magnetoresistive elements'
[patent_app_type] => B2
[patent_app_number] => 09/985968
[patent_app_country] => US
[patent_app_date] => 2001-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 6729
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/522/06522575.pdf
[firstpage_image] =>[orig_patent_app_number] => 09985968
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/985968 | Semiconductor memory device having magnetoresistive elements | Nov 6, 2001 | Issued |
Array
(
[id] => 6287827
[patent_doc_number] => 20020054500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-09
[patent_title] => 'Magnetic memory device including storage element exhibiting ferromagnetic tunnel effect'
[patent_app_type] => new
[patent_app_number] => 09/985770
[patent_app_country] => US
[patent_app_date] => 2001-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 13799
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20020054500.pdf
[firstpage_image] =>[orig_patent_app_number] => 09985770
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/985770 | Magnetic memory device including storage element exhibiting ferromagnetic tunnel effect | Nov 5, 2001 | Issued |
Array
(
[id] => 1413733
[patent_doc_number] => 06542416
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Methods and arrangements for conditionally enforcing CAS latencies in memory devices'
[patent_app_type] => B1
[patent_app_number] => 10/001030
[patent_app_country] => US
[patent_app_date] => 2001-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2687
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/542/06542416.pdf
[firstpage_image] =>[orig_patent_app_number] => 10001030
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/001030 | Methods and arrangements for conditionally enforcing CAS latencies in memory devices | Nov 1, 2001 | Issued |
Array
(
[id] => 1396274
[patent_doc_number] => 06560152
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Non-volatile memory with temperature-compensated data read'
[patent_app_type] => B1
[patent_app_number] => 10/053171
[patent_app_country] => US
[patent_app_date] => 2001-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4278
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/560/06560152.pdf
[firstpage_image] =>[orig_patent_app_number] => 10053171
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/053171 | Non-volatile memory with temperature-compensated data read | Nov 1, 2001 | Issued |
Array
(
[id] => 6790982
[patent_doc_number] => 20030086326
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-08
[patent_title] => 'Non-volatile flash fuse element'
[patent_app_type] => new
[patent_app_number] => 10/002036
[patent_app_country] => US
[patent_app_date] => 2001-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10909
[patent_no_of_claims] => 95
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20030086326.pdf
[firstpage_image] =>[orig_patent_app_number] => 10002036
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/002036 | Non-volatile flash fuse element | Oct 31, 2001 | Issued |
Array
(
[id] => 7644617
[patent_doc_number] => 06473356
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-29
[patent_title] => 'Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier'
[patent_app_type] => B1
[patent_app_number] => 10/002568
[patent_app_country] => US
[patent_app_date] => 2001-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 7353
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/473/06473356.pdf
[firstpage_image] =>[orig_patent_app_number] => 10002568
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/002568 | Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier | Oct 31, 2001 | Issued |
Array
(
[id] => 1431641
[patent_doc_number] => 06504742
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => '3-D memory device for large storage capacity'
[patent_app_type] => B1
[patent_app_number] => 09/984934
[patent_app_country] => US
[patent_app_date] => 2001-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3592
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/504/06504742.pdf
[firstpage_image] =>[orig_patent_app_number] => 09984934
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/984934 | 3-D memory device for large storage capacity | Oct 30, 2001 | Issued |
Array
(
[id] => 1454315
[patent_doc_number] => 06456524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Hybrid resistive cross point memory cell arrays and methods of making the same'
[patent_app_type] => B1
[patent_app_number] => 10/000636
[patent_app_country] => US
[patent_app_date] => 2001-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4090
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/456/06456524.pdf
[firstpage_image] =>[orig_patent_app_number] => 10000636
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/000636 | Hybrid resistive cross point memory cell arrays and methods of making the same | Oct 30, 2001 | Issued |
| 09/984870 | PRIORITY ENCODER CIRCUIT AND METHOD FOR CONTENT ADDRESSABLE MEMORY | Oct 30, 2001 | Abandoned |
Array
(
[id] => 6287897
[patent_doc_number] => 20020054517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-09
[patent_title] => 'Sequence circuit and semiconductor device using sequence circuit'
[patent_app_type] => new
[patent_app_number] => 09/984270
[patent_app_country] => US
[patent_app_date] => 2001-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4851
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20020054517.pdf
[firstpage_image] =>[orig_patent_app_number] => 09984270
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/984270 | Sequence circuit and semiconductor device using sequence circuit | Oct 28, 2001 | Issued |
Array
(
[id] => 1342065
[patent_doc_number] => 06597610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-22
[patent_title] => 'System and method for providing stability for a low power static random access memory cell'
[patent_app_type] => B2
[patent_app_number] => 09/999030
[patent_app_country] => US
[patent_app_date] => 2001-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 3289
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/597/06597610.pdf
[firstpage_image] =>[orig_patent_app_number] => 09999030
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/999030 | System and method for providing stability for a low power static random access memory cell | Oct 24, 2001 | Issued |
Array
(
[id] => 1454481
[patent_doc_number] => 06456563
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Semiconductor memory device that operates in sychronization with a clock signal'
[patent_app_type] => B1
[patent_app_number] => 09/983632
[patent_app_country] => US
[patent_app_date] => 2001-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8145
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/456/06456563.pdf
[firstpage_image] =>[orig_patent_app_number] => 09983632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/983632 | Semiconductor memory device that operates in sychronization with a clock signal | Oct 24, 2001 | Issued |