Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1442527 [patent_doc_number] => 06496399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Compact ternary content addressable memory cell' [patent_app_type] => B1 [patent_app_number] => 09/941372 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6310 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496399.pdf [firstpage_image] =>[orig_patent_app_number] => 09941372 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941372
Compact ternary content addressable memory cell Aug 27, 2001 Issued
Array ( [id] => 1426129 [patent_doc_number] => 06510080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Three terminal magnetic random access memory' [patent_app_type] => B1 [patent_app_number] => 09/940976 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 40 [patent_no_of_words] => 8878 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510080.pdf [firstpage_image] =>[orig_patent_app_number] => 09940976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940976
Three terminal magnetic random access memory Aug 27, 2001 Issued
Array ( [id] => 1429548 [patent_doc_number] => 06515928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor memory device having a plurality of low power consumption modes' [patent_app_type] => B2 [patent_app_number] => 09/939735 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 11238 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515928.pdf [firstpage_image] =>[orig_patent_app_number] => 09939735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939735
Semiconductor memory device having a plurality of low power consumption modes Aug 27, 2001 Issued
Array ( [id] => 1359265 [patent_doc_number] => 06584030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Memory circuit regulation system and method' [patent_app_type] => B2 [patent_app_number] => 09/941130 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 8345 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584030.pdf [firstpage_image] =>[orig_patent_app_number] => 09941130 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941130
Memory circuit regulation system and method Aug 27, 2001 Issued
Array ( [id] => 6691733 [patent_doc_number] => 20030039165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'High performance semiconductor memory devices' [patent_app_type] => new [patent_app_number] => 09/938431 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8272 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20030039165.pdf [firstpage_image] =>[orig_patent_app_number] => 09938431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938431
High performance semiconductor memory devices Aug 22, 2001 Issued
Array ( [id] => 5870659 [patent_doc_number] => 20020047181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor integrated circuit device with electrically programmable fuse' [patent_app_type] => new [patent_app_number] => 09/934834 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047181.pdf [firstpage_image] =>[orig_patent_app_number] => 09934834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/934834
Semiconductor integrated circuit device with electrically programmable fuse Aug 22, 2001 Issued
Array ( [id] => 1550313 [patent_doc_number] => 06445631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Non-volatile latch with program strength verification' [patent_app_type] => B1 [patent_app_number] => 09/938397 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5012 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445631.pdf [firstpage_image] =>[orig_patent_app_number] => 09938397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938397
Non-volatile latch with program strength verification Aug 22, 2001 Issued
Array ( [id] => 1407049 [patent_doc_number] => 06549470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays' [patent_app_type] => B2 [patent_app_number] => 09/932331 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4671 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549470.pdf [firstpage_image] =>[orig_patent_app_number] => 09932331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932331
Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays Aug 16, 2001 Issued
Array ( [id] => 6239879 [patent_doc_number] => 20020044489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Semiconductor memory device with redundancy logic cell and repair method' [patent_app_type] => new [patent_app_number] => 09/929930 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4652 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20020044489.pdf [firstpage_image] =>[orig_patent_app_number] => 09929930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929930
Semiconductor memory device with redundancy logic cell and repair method Aug 14, 2001 Issued
Array ( [id] => 1425604 [patent_doc_number] => 06525953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/928536 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 11079 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525953.pdf [firstpage_image] =>[orig_patent_app_number] => 09928536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928536
Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication Aug 12, 2001 Issued
Array ( [id] => 1461069 [patent_doc_number] => 06426889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/923542 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 9405 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426889.pdf [firstpage_image] =>[orig_patent_app_number] => 09923542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923542
Semiconductor integrated circuit Aug 7, 2001 Issued
Array ( [id] => 1538574 [patent_doc_number] => 06490200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Non-volatile memory with improved sensing and method therefor' [patent_app_type] => B2 [patent_app_number] => 09/924410 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 8340 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490200.pdf [firstpage_image] =>[orig_patent_app_number] => 09924410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924410
Non-volatile memory with improved sensing and method therefor Aug 6, 2001 Issued
Array ( [id] => 6714789 [patent_doc_number] => 20030026137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => ' Method and apparatus for determining digital delay line entry point' [patent_app_type] => new [patent_app_number] => 09/923136 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5264 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20030026137.pdf [firstpage_image] =>[orig_patent_app_number] => 09923136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923136
Method and apparatus for determining digital delay line entry point Aug 5, 2001 Issued
Array ( [id] => 6714801 [patent_doc_number] => 20030026149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'DYNAMIC PRECHARGE DECODE SCHEME FOR FAST DRAM' [patent_app_type] => new [patent_app_number] => 09/918830 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20030026149.pdf [firstpage_image] =>[orig_patent_app_number] => 09918830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918830
Dynamic precharge decode scheme for fast DRAM Jul 31, 2001 Issued
Array ( [id] => 6466654 [patent_doc_number] => 20020021598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Nonvolatile memory, system having nonvolatile memories, and data read method of the system' [patent_app_type] => new [patent_app_number] => 09/916735 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5653 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021598.pdf [firstpage_image] =>[orig_patent_app_number] => 09916735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916735
Nonvolatile memory, system having nonvolatile memories, and data read method of the system Jul 25, 2001 Issued
Array ( [id] => 6743960 [patent_doc_number] => 20030021143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'FERROELECTRIC MEMORY AND METHOD FOR READING THE SAME' [patent_app_type] => new [patent_app_number] => 09/912634 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4690 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20030021143.pdf [firstpage_image] =>[orig_patent_app_number] => 09912634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/912634
Ferroelectric memory and method for reading the same Jul 23, 2001 Issued
Array ( [id] => 1427933 [patent_doc_number] => 06519197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Sense amplifier with improved read access' [patent_app_type] => B2 [patent_app_number] => 09/912622 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9993 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519197.pdf [firstpage_image] =>[orig_patent_app_number] => 09912622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/912622
Sense amplifier with improved read access Jul 23, 2001 Issued
Array ( [id] => 1585312 [patent_doc_number] => 06424562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Read/write architecture for MRAM' [patent_app_type] => B1 [patent_app_number] => 09/905830 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5126 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424562.pdf [firstpage_image] =>[orig_patent_app_number] => 09905830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905830
Read/write architecture for MRAM Jul 12, 2001 Issued
Array ( [id] => 1372440 [patent_doc_number] => 06574148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Dual bit line driver for memory' [patent_app_type] => B2 [patent_app_number] => 09/904233 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2602 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574148.pdf [firstpage_image] =>[orig_patent_app_number] => 09904233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904233
Dual bit line driver for memory Jul 11, 2001 Issued
Array ( [id] => 1427796 [patent_doc_number] => 06519182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure' [patent_app_type] => B1 [patent_app_number] => 09/902332 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4085 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519182.pdf [firstpage_image] =>[orig_patent_app_number] => 09902332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902332
Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure Jul 9, 2001 Issued
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