Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1423556 [patent_doc_number] => 06529408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Semiconductor storage device and method for evaluating the same' [patent_app_type] => B2 [patent_app_number] => 09/903136 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11222 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529408.pdf [firstpage_image] =>[orig_patent_app_number] => 09903136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903136
Semiconductor storage device and method for evaluating the same Jul 9, 2001 Issued
Array ( [id] => 1504378 [patent_doc_number] => 06487133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/898033 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 6200 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487133.pdf [firstpage_image] =>[orig_patent_app_number] => 09898033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898033
Semiconductor device Jul 4, 2001 Issued
Array ( [id] => 6285822 [patent_doc_number] => 20020053944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration' [patent_app_type] => new [patent_app_number] => 09/898233 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1549 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053944.pdf [firstpage_image] =>[orig_patent_app_number] => 09898233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898233
Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration Jul 2, 2001 Issued
Array ( [id] => 1431700 [patent_doc_number] => 06504766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'System and method for early write to memory by injecting small voltage signal' [patent_app_type] => B1 [patent_app_number] => 09/896734 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4136 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504766.pdf [firstpage_image] =>[orig_patent_app_number] => 09896734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896734
System and method for early write to memory by injecting small voltage signal Jun 28, 2001 Issued
Array ( [id] => 1397963 [patent_doc_number] => 06556471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'VDD modulated SRAM for highly scaled, high performance cache' [patent_app_type] => B2 [patent_app_number] => 09/893236 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5679 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556471.pdf [firstpage_image] =>[orig_patent_app_number] => 09893236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893236
VDD modulated SRAM for highly scaled, high performance cache Jun 26, 2001 Issued
Array ( [id] => 1454477 [patent_doc_number] => 06456562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Clock generation circuits' [patent_app_type] => B1 [patent_app_number] => 09/892099 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8607 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456562.pdf [firstpage_image] =>[orig_patent_app_number] => 09892099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892099
Clock generation circuits Jun 25, 2001 Issued
Array ( [id] => 6597249 [patent_doc_number] => 20020085431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Redundancy circuit of semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/884536 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4206 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085431.pdf [firstpage_image] =>[orig_patent_app_number] => 09884536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884536
Redundancy circuit of semiconductor memory device Jun 18, 2001 Issued
Array ( [id] => 1493397 [patent_doc_number] => 06418065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-09 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 09/883236 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 12899 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418065.pdf [firstpage_image] =>[orig_patent_app_number] => 09883236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/883236
Nonvolatile semiconductor memory Jun 18, 2001 Issued
Array ( [id] => 1418965 [patent_doc_number] => 06535437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Block redundancy in ultra low power memory circuits' [patent_app_type] => B1 [patent_app_number] => 09/882898 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2648 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535437.pdf [firstpage_image] =>[orig_patent_app_number] => 09882898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882898
Block redundancy in ultra low power memory circuits Jun 14, 2001 Issued
Array ( [id] => 1531166 [patent_doc_number] => 06480422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Contactless flash memory with shared buried diffusion bit line architecture' [patent_app_type] => B1 [patent_app_number] => 09/882136 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5430 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480422.pdf [firstpage_image] =>[orig_patent_app_number] => 09882136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882136
Contactless flash memory with shared buried diffusion bit line architecture Jun 13, 2001 Issued
Array ( [id] => 1401759 [patent_doc_number] => 06552923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'SRAM with write-back on read' [patent_app_type] => B2 [patent_app_number] => 09/877534 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4736 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552923.pdf [firstpage_image] =>[orig_patent_app_number] => 09877534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/877534
SRAM with write-back on read Jun 7, 2001 Issued
Array ( [id] => 1473332 [patent_doc_number] => 06407959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-18 [patent_title] => 'Microcomputer and microprocessor having flash memory operable from single external power supply' [patent_app_type] => B2 [patent_app_number] => 09/874116 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 14448 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407959.pdf [firstpage_image] =>[orig_patent_app_number] => 09874116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874116
Microcomputer and microprocessor having flash memory operable from single external power supply Jun 5, 2001 Issued
Array ( [id] => 1398357 [patent_doc_number] => 06556491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Semiconductor storage device and method of testing the same' [patent_app_type] => B2 [patent_app_number] => 09/871932 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5639 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556491.pdf [firstpage_image] =>[orig_patent_app_number] => 09871932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871932
Semiconductor storage device and method of testing the same May 31, 2001 Issued
Array ( [id] => 6395732 [patent_doc_number] => 20020181286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'DUAL CELL READING AND WRITING TECHNIQUE' [patent_app_type] => new [patent_app_number] => 09/871332 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7150 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20020181286.pdf [firstpage_image] =>[orig_patent_app_number] => 09871332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871332
Dual cell reading and writing technique May 30, 2001 Issued
Array ( [id] => 6590606 [patent_doc_number] => 20020015332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Circuital structure for reading data in a non-volatile memory device' [patent_app_type] => new [patent_app_number] => 09/871234 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2272 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20020015332.pdf [firstpage_image] =>[orig_patent_app_number] => 09871234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871234
Circuital structure for reading data in a non-volatile memory device May 29, 2001 Issued
Array ( [id] => 6395788 [patent_doc_number] => 20020181293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'TRCD MARGIN' [patent_app_type] => new [patent_app_number] => 09/867734 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20020181293.pdf [firstpage_image] =>[orig_patent_app_number] => 09867734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867734
tRCD margin May 29, 2001 Issued
Array ( [id] => 6395596 [patent_doc_number] => 20020181271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Dynamic random access memory cell' [patent_app_type] => new [patent_app_number] => 09/865736 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1935 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20020181271.pdf [firstpage_image] =>[orig_patent_app_number] => 09865736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865736
Dynamic random access memory cell May 28, 2001 Abandoned
Array ( [id] => 6435433 [patent_doc_number] => 20020176272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'SELECT LINE ARCHITECTURE FOR MAGNETIC RANDOM ACCESS MEMORIES' [patent_app_type] => new [patent_app_number] => 09/863730 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7437 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20020176272.pdf [firstpage_image] =>[orig_patent_app_number] => 09863730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863730
Select line architecture for magnetic random access memories May 22, 2001 Issued
Array ( [id] => 6294451 [patent_doc_number] => 20020056051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Apparatus and method for reading the default value of a peripheral component' [patent_app_type] => new [patent_app_number] => 09/861931 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4171 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056051.pdf [firstpage_image] =>[orig_patent_app_number] => 09861931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861931
Apparatus and method for reading the default value of a peripheral component May 20, 2001 Issued
Array ( [id] => 1426177 [patent_doc_number] => 06510085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method of channel hot electron programming for short channel NOR flash arrays' [patent_app_type] => B1 [patent_app_number] => 09/861031 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4199 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510085.pdf [firstpage_image] =>[orig_patent_app_number] => 09861031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861031
Method of channel hot electron programming for short channel NOR flash arrays May 17, 2001 Issued
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