Dirk Wright

Array ( [id] => 1578361 [patent_doc_number] => 06469945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Dynamically configurated storage array with improved data access' [patent_app_type] => B2 [patent_app_number] => 09/861076 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6238 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469945.pdf [firstpage_image] =>[orig_patent_app_number] => 09861076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1470087 [patent_doc_number] => 06459650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method and apparatus for asynchronously controlling a DRAM array in a SRAM environment' [patent_app_type] => B1 [patent_app_number] => 09/858832 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2746 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459650.pdf [firstpage_image] =>[orig_patent_app_number] => 09858832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1599678 [patent_doc_number] => 06385091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Read reference scheme for non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 09/846936 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4634 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385091.pdf [firstpage_image] =>[orig_patent_app_number] => 09846936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1546834 [patent_doc_number] => 06373748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/842406 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 31106 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373748.pdf [firstpage_image] =>[orig_patent_app_number] => 09842406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6985544 [patent_doc_number] => 20010035537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/839306 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6490 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20010035537.pdf [firstpage_image] =>[orig_patent_app_number] => 09839306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6094346 [patent_doc_number] => 20020051393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'SEMICONDUCTOR MEMORY PROVIDED WITH DATA-LINE EQUALIZING CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/839403 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9442 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20020051393.pdf [firstpage_image] =>[orig_patent_app_number] => 09839403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1599723 [patent_doc_number] => 06385104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Semiconductor memory device having a test mode decision circuit' [patent_app_type] => B2 [patent_app_number] => 09/839504 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3919 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385104.pdf [firstpage_image] =>[orig_patent_app_number] => 09839504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418716 [patent_doc_number] => 06535417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Semiconductor storage device' [patent_app_type] => B2 [patent_app_number] => 09/837233 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9538 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535417.pdf [firstpage_image] =>[orig_patent_app_number] => 09837233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1463743 [patent_doc_number] => 06392934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for reading and writing a data storage medium comprising a material with a succession of zones having a first and second physical state respectively' [patent_app_type] => B1 [patent_app_number] => 09/807808 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4500 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392934.pdf [firstpage_image] =>[orig_patent_app_number] => 09807808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7642954 [patent_doc_number] => 06430092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Memory device with booting circuit capable of pre-booting before wordline selection' [patent_app_type] => B2 [patent_app_number] => 09/834402 [patent_app_country] => US [patent_app_date] => 2001-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3645 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430092.pdf [firstpage_image] =>[orig_patent_app_number] => 09834402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416600 [patent_doc_number] => 06538913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method for operating a ferroelectric memory configuration and a ferroelectric memory configuration' [patent_app_type] => B2 [patent_app_number] => 09/826232 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2742 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538913.pdf [firstpage_image] =>[orig_patent_app_number] => 09826232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6223010 [patent_doc_number] => 20020003719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 09/824232 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7485 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003719.pdf [firstpage_image] =>[orig_patent_app_number] => 09824232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1499253 [patent_doc_number] => 06404689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline' [patent_app_type] => B1 [patent_app_number] => 09/822430 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4883 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404689.pdf [firstpage_image] =>[orig_patent_app_number] => 09822430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5903601 [patent_doc_number] => 20020141253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'SELECTIVE FORWARDING OF A STROBE BASED ON A PREDETERMINED DELAY FOLLOWING A MEMORY READ COMMAND' [patent_app_type] => new [patent_app_number] => 09/823533 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3749 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20020141253.pdf [firstpage_image] =>[orig_patent_app_number] => 09823533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1465194 [patent_doc_number] => 06351415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Symmetrical non-volatile memory array architecture without neighbor effect' [patent_app_type] => B1 [patent_app_number] => 09/821336 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351415.pdf [firstpage_image] =>[orig_patent_app_number] => 09821336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6884403 [patent_doc_number] => 20010038562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Integrated memory having a differential sense amplifier' [patent_app_type] => new [patent_app_number] => 09/820235 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4270 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038562.pdf [firstpage_image] =>[orig_patent_app_number] => 09820235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6109139 [patent_doc_number] => 20020172072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Molecular memory systems and methods' [patent_app_type] => new [patent_app_number] => 09/819402 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3201 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20020172072.pdf [firstpage_image] =>[orig_patent_app_number] => 09819402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6895702 [patent_doc_number] => 20010026492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor memory device with a refresh function' [patent_app_type] => new [patent_app_number] => 09/815802 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5255 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026492.pdf [firstpage_image] =>[orig_patent_app_number] => 09815802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6888942 [patent_doc_number] => 20010024397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/816609 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2541 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024397.pdf [firstpage_image] =>[orig_patent_app_number] => 09816609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6239873 [patent_doc_number] => 20020044486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'IC card with different page sizes to increase endurance' [patent_app_type] => new [patent_app_number] => 09/814934 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2495 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20020044486.pdf [firstpage_image] =>[orig_patent_app_number] => 09814934 [rel_patent_id] =>[rel_patent_doc_number] =>)