Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1546943 [patent_doc_number] => 06373774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor memory device with bank configuration' [patent_app_type] => B1 [patent_app_number] => 09/773710 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9009 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373774.pdf [firstpage_image] =>[orig_patent_app_number] => 09773710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773710
Semiconductor memory device with bank configuration Feb 1, 2001 Issued
Array ( [id] => 1564362 [patent_doc_number] => 06438067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same' [patent_app_type] => B2 [patent_app_number] => 09/773637 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6996 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438067.pdf [firstpage_image] =>[orig_patent_app_number] => 09773637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773637
Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same Feb 1, 2001 Issued
Array ( [id] => 1570346 [patent_doc_number] => 06377491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-23 [patent_title] => 'Non-volatile memory for storing erase operation information' [patent_app_type] => B2 [patent_app_number] => 09/774632 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3477 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377491.pdf [firstpage_image] =>[orig_patent_app_number] => 09774632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774632
Non-volatile memory for storing erase operation information Jan 31, 2001 Issued
Array ( [id] => 4393039 [patent_doc_number] => 06304477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Content addressable magnetic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/774934 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3200 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304477.pdf [firstpage_image] =>[orig_patent_app_number] => 774934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774934
Content addressable magnetic random access memory Jan 30, 2001 Issued
Array ( [id] => 4318171 [patent_doc_number] => 06327211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Inverter having a variable threshold potential' [patent_app_type] => 1 [patent_app_number] => 9/769414 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 11445 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327211.pdf [firstpage_image] =>[orig_patent_app_number] => 769414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769414
Inverter having a variable threshold potential Jan 25, 2001 Issued
Array ( [id] => 1499241 [patent_doc_number] => 06404686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/770912 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2374 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404686.pdf [firstpage_image] =>[orig_patent_app_number] => 09770912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770912
High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus Jan 25, 2001 Issued
Array ( [id] => 6061934 [patent_doc_number] => 20020031006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => ' Semiconductor memory device having improved memory cell and bit line pitch' [patent_app_type] => new [patent_app_number] => 09/769416 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10526 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031006.pdf [firstpage_image] =>[orig_patent_app_number] => 09769416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769416
Semiconductor memory device having improved memory cell and bit line pitch Jan 25, 2001 Issued
Array ( [id] => 1450031 [patent_doc_number] => 06370067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Automatic configuration of delay parameters in a dynamic memory controller' [patent_app_type] => B1 [patent_app_number] => 09/772111 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2837 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370067.pdf [firstpage_image] =>[orig_patent_app_number] => 09772111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772111
Automatic configuration of delay parameters in a dynamic memory controller Jan 24, 2001 Issued
Array ( [id] => 1546930 [patent_doc_number] => 06373771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Integrated fuse latch and shift register for efficient programming and fuse readout' [patent_app_type] => B1 [patent_app_number] => 09/765035 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7742 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373771.pdf [firstpage_image] =>[orig_patent_app_number] => 09765035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765035
Integrated fuse latch and shift register for efficient programming and fuse readout Jan 16, 2001 Issued
Array ( [id] => 1589942 [patent_doc_number] => 06359803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Semiconductor memory device that can access two regions alternately at high speed' [patent_app_type] => B1 [patent_app_number] => 09/759319 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10881 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359803.pdf [firstpage_image] =>[orig_patent_app_number] => 09759319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759319
Semiconductor memory device that can access two regions alternately at high speed Jan 15, 2001 Issued
Array ( [id] => 4407230 [patent_doc_number] => 06298003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Boost circuit of DRAM with variable loading' [patent_app_type] => 1 [patent_app_number] => 9/758931 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2615 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298003.pdf [firstpage_image] =>[orig_patent_app_number] => 758931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758931
Boost circuit of DRAM with variable loading Jan 10, 2001 Issued
Array ( [id] => 1496446 [patent_doc_number] => 06343039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-29 [patent_title] => 'Data transfer circuit' [patent_app_type] => B2 [patent_app_number] => 09/754131 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343039.pdf [firstpage_image] =>[orig_patent_app_number] => 09754131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754131
Data transfer circuit Jan 4, 2001 Issued
Array ( [id] => 6884401 [patent_doc_number] => 20010038560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Semiconductor memory device for reducing parasitic resistance of the I/O lines' [patent_app_type] => new [patent_app_number] => 09/754119 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3444 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038560.pdf [firstpage_image] =>[orig_patent_app_number] => 09754119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754119
Semiconductor memory device for reducing parasitic resistance of the I/O lines Jan 4, 2001 Issued
Array ( [id] => 7013413 [patent_doc_number] => 20010050868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Semiconductor memory device with redundancy circuit' [patent_app_type] => new [patent_app_number] => 09/753516 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7222 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20010050868.pdf [firstpage_image] =>[orig_patent_app_number] => 09753516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753516
Semiconductor memory device with redundancy circuit Jan 3, 2001 Issued
Array ( [id] => 693372 [patent_doc_number] => 07075827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/754632 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 112 [patent_figures_cnt] => 131 [patent_no_of_words] => 51720 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075827.pdf [firstpage_image] =>[orig_patent_app_number] => 09754632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754632
Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device Jan 3, 2001 Issued
Array ( [id] => 6597093 [patent_doc_number] => 20020085424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Local sensing of non-volatile memory' [patent_app_type] => new [patent_app_number] => 09/752936 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2133 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085424.pdf [firstpage_image] =>[orig_patent_app_number] => 09752936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752936
Local sensing of non-volatile memory Dec 28, 2000 Issued
Array ( [id] => 4419392 [patent_doc_number] => 06301176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Asynchronous memory self time scheme' [patent_app_type] => 1 [patent_app_number] => 9/750214 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3623 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301176.pdf [firstpage_image] =>[orig_patent_app_number] => 750214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750214
Asynchronous memory self time scheme Dec 26, 2000 Issued
Array ( [id] => 4283466 [patent_doc_number] => 06307803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Dynamic random access memory suitable for use as a compatible transistor of a static random access memory and the method for operating the same' [patent_app_type] => 1 [patent_app_number] => 9/749358 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5036 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307803.pdf [firstpage_image] =>[orig_patent_app_number] => 749358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749358
Dynamic random access memory suitable for use as a compatible transistor of a static random access memory and the method for operating the same Dec 26, 2000 Issued
Array ( [id] => 1418633 [patent_doc_number] => 06535411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Memory module and computer system comprising a memory module' [patent_app_type] => B2 [patent_app_number] => 09/747936 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3049 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535411.pdf [firstpage_image] =>[orig_patent_app_number] => 09747936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747936
Memory module and computer system comprising a memory module Dec 26, 2000 Issued
Array ( [id] => 7040526 [patent_doc_number] => 20010005327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Negative resistance device' [patent_app_type] => new-utility [patent_app_number] => 09/742214 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3758 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005327.pdf [firstpage_image] =>[orig_patent_app_number] => 09742214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742214
Negative resistance device Dec 21, 2000 Issued
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