Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4395270 [patent_doc_number] => 06278637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'SRAM generating an echo clock signal' [patent_app_type] => 1 [patent_app_number] => 9/632832 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 6030 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278637.pdf [firstpage_image] =>[orig_patent_app_number] => 632832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632832
SRAM generating an echo clock signal Aug 3, 2000 Issued
Array ( [id] => 4273414 [patent_doc_number] => 06259639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory' [patent_app_type] => 1 [patent_app_number] => 9/630432 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 25060 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259639.pdf [firstpage_image] =>[orig_patent_app_number] => 630432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630432
Semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory Jul 31, 2000 Issued
Array ( [id] => 4283045 [patent_doc_number] => 06307773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Non-volatile latch with program strength verification' [patent_app_type] => 1 [patent_app_number] => 9/627530 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5007 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307773.pdf [firstpage_image] =>[orig_patent_app_number] => 627530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627530
Non-volatile latch with program strength verification Jul 27, 2000 Issued
Array ( [id] => 4283131 [patent_doc_number] => 06307779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method and circuitry for bank tracking in write command sequence' [patent_app_type] => 1 [patent_app_number] => 9/628734 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 13505 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307779.pdf [firstpage_image] =>[orig_patent_app_number] => 628734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628734
Method and circuitry for bank tracking in write command sequence Jul 27, 2000 Issued
Array ( [id] => 4367139 [patent_doc_number] => 06292417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Memory device with reduced bit line pre-charge voltage' [patent_app_type] => 1 [patent_app_number] => 9/626211 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3432 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292417.pdf [firstpage_image] =>[orig_patent_app_number] => 626211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626211
Memory device with reduced bit line pre-charge voltage Jul 25, 2000 Issued
Array ( [id] => 4359022 [patent_doc_number] => 06285606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/621705 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 14154 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285606.pdf [firstpage_image] =>[orig_patent_app_number] => 621705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621705
Semiconductor memory device Jul 23, 2000 Issued
Array ( [id] => 4305006 [patent_doc_number] => 06236590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Optimal write conductors layout for improved performance in MRAM' [patent_app_type] => 1 [patent_app_number] => 9/624134 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 8540 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236590.pdf [firstpage_image] =>[orig_patent_app_number] => 624134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624134
Optimal write conductors layout for improved performance in MRAM Jul 20, 2000 Issued
Array ( [id] => 1600059 [patent_doc_number] => 06493258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Magneto-resistive memory array' [patent_app_type] => B1 [patent_app_number] => 09/618237 [patent_app_country] => US [patent_app_date] => 2000-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10093 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493258.pdf [firstpage_image] =>[orig_patent_app_number] => 09618237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618237
Magneto-resistive memory array Jul 17, 2000 Issued
Array ( [id] => 4273220 [patent_doc_number] => 06259626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for storing bytes in multi-level non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 9/616507 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2474 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259626.pdf [firstpage_image] =>[orig_patent_app_number] => 616507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/616507
Method for storing bytes in multi-level non-volatile memory cells Jul 13, 2000 Issued
Array ( [id] => 1496421 [patent_doc_number] => 06343032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Non-volatile spin dependent tunnel junction circuit' [patent_app_type] => B1 [patent_app_number] => 09/610503 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5019 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343032.pdf [firstpage_image] =>[orig_patent_app_number] => 09610503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610503
Non-volatile spin dependent tunnel junction circuit Jul 5, 2000 Issued
Array ( [id] => 1285534 [patent_doc_number] => 06646953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Single-clock, strobeless signaling system' [patent_app_type] => B1 [patent_app_number] => 09/611936 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9253 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646953.pdf [firstpage_image] =>[orig_patent_app_number] => 09611936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/611936
Single-clock, strobeless signaling system Jul 5, 2000 Issued
Array ( [id] => 4395434 [patent_doc_number] => 06278649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Bank selection structures for a memory array, including a flat cell ROM array' [patent_app_type] => 1 [patent_app_number] => 9/607730 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6662 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278649.pdf [firstpage_image] =>[orig_patent_app_number] => 607730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607730
Bank selection structures for a memory array, including a flat cell ROM array Jun 29, 2000 Issued
Array ( [id] => 4366793 [patent_doc_number] => 06292394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for programming of a semiconductor memory cell' [patent_app_type] => 1 [patent_app_number] => 9/606205 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3793 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292394.pdf [firstpage_image] =>[orig_patent_app_number] => 606205 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606205
Method for programming of a semiconductor memory cell Jun 28, 2000 Issued
Array ( [id] => 1288286 [patent_doc_number] => 06643190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Packet command driving type memory device' [patent_app_type] => B1 [patent_app_number] => 09/604337 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5169 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643190.pdf [firstpage_image] =>[orig_patent_app_number] => 09604337 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604337
Packet command driving type memory device Jun 26, 2000 Issued
Array ( [id] => 4298666 [patent_doc_number] => 06269040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Interconnection network for connecting memory cells to sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 9/603632 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12123 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269040.pdf [firstpage_image] =>[orig_patent_app_number] => 603632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603632
Interconnection network for connecting memory cells to sense amplifiers Jun 25, 2000 Issued
Array ( [id] => 1552266 [patent_doc_number] => 06347055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Line buffer type semiconductor memory device capable of direct prefetch and restore operations' [patent_app_type] => B1 [patent_app_number] => 09/599930 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4669 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347055.pdf [firstpage_image] =>[orig_patent_app_number] => 09599930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599930
Line buffer type semiconductor memory device capable of direct prefetch and restore operations Jun 21, 2000 Issued
Array ( [id] => 1437705 [patent_doc_number] => 06356498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Selective power distribution circuit for an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/597393 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6883 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356498.pdf [firstpage_image] =>[orig_patent_app_number] => 09597393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597393
Selective power distribution circuit for an integrated circuit Jun 18, 2000 Issued
Array ( [id] => 4291221 [patent_doc_number] => 06282140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Multiplexor having a single event upset (SEU) immune data keeper circuit' [patent_app_type] => 1 [patent_app_number] => 9/589732 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3327 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282140.pdf [firstpage_image] =>[orig_patent_app_number] => 589732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/589732
Multiplexor having a single event upset (SEU) immune data keeper circuit Jun 7, 2000 Issued
Array ( [id] => 4263117 [patent_doc_number] => 06222793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Memory devices having a restore start address counter' [patent_app_type] => 1 [patent_app_number] => 9/587930 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4381 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222793.pdf [firstpage_image] =>[orig_patent_app_number] => 587930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/587930
Memory devices having a restore start address counter Jun 5, 2000 Issued
Array ( [id] => 4383997 [patent_doc_number] => 06288928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor integrated circuit and method of controlling column switch of semiconductor integrated circuit in write operation' [patent_app_type] => 1 [patent_app_number] => 9/588230 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12254 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288928.pdf [firstpage_image] =>[orig_patent_app_number] => 588230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588230
Semiconductor integrated circuit and method of controlling column switch of semiconductor integrated circuit in write operation Jun 5, 2000 Issued
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