Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1567609 [patent_doc_number] => 06339543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Writing method for a magnetic immovable memory and a magnetic immovable memory' [patent_app_type] => B1 [patent_app_number] => 09/580634 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1863 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339543.pdf [firstpage_image] =>[orig_patent_app_number] => 09580634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/580634
Writing method for a magnetic immovable memory and a magnetic immovable memory May 29, 2000 Issued
Array ( [id] => 4305167 [patent_doc_number] => 06236602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Dynamic configuration of storage arrays' [patent_app_type] => 1 [patent_app_number] => 9/580936 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5441 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236602.pdf [firstpage_image] =>[orig_patent_app_number] => 580936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/580936
Dynamic configuration of storage arrays May 24, 2000 Issued
Array ( [id] => 4395324 [patent_doc_number] => 06278641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus capable of programmably delaying clock of DRAM' [patent_app_type] => 1 [patent_app_number] => 9/578234 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3243 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278641.pdf [firstpage_image] =>[orig_patent_app_number] => 578234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578234
Method and apparatus capable of programmably delaying clock of DRAM May 23, 2000 Issued
Array ( [id] => 4393311 [patent_doc_number] => 06304495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Logic interface circuit and semiconductor memory device using this circuit' [patent_app_type] => 1 [patent_app_number] => 9/576936 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7156 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304495.pdf [firstpage_image] =>[orig_patent_app_number] => 576936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576936
Logic interface circuit and semiconductor memory device using this circuit May 21, 2000 Issued
Array ( [id] => 4305234 [patent_doc_number] => 06236607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Integrated memory having a reference potential and operating method for such a memory' [patent_app_type] => 1 [patent_app_number] => 9/574701 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4333 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236607.pdf [firstpage_image] =>[orig_patent_app_number] => 574701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574701
Integrated memory having a reference potential and operating method for such a memory May 17, 2000 Issued
Array ( [id] => 4419083 [patent_doc_number] => 06301152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Non-volatile memory device with row redundancy' [patent_app_type] => 1 [patent_app_number] => 9/570332 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2711 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301152.pdf [firstpage_image] =>[orig_patent_app_number] => 570332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570332
Non-volatile memory device with row redundancy May 11, 2000 Issued
Array ( [id] => 4366852 [patent_doc_number] => 06292398 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for the in-writing verification of the threshold value in non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 9/569232 [patent_app_country] => US [patent_app_date] => 2000-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292398.pdf [firstpage_image] =>[orig_patent_app_number] => 569232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569232
Method for the in-writing verification of the threshold value in non-volatile memories May 10, 2000 Issued
Array ( [id] => 4419065 [patent_doc_number] => 06301150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell' [patent_app_type] => 1 [patent_app_number] => 9/561210 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 49 [patent_no_of_words] => 19318 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301150.pdf [firstpage_image] =>[orig_patent_app_number] => 561210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561210
Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell Apr 27, 2000 Issued
Array ( [id] => 4420204 [patent_doc_number] => 06266292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'DRAM core refresh with reduced spike current' [patent_app_type] => 1 [patent_app_number] => 9/561603 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4427 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266292.pdf [firstpage_image] =>[orig_patent_app_number] => 561603 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561603
DRAM core refresh with reduced spike current Apr 26, 2000 Issued
Array ( [id] => 1496455 [patent_doc_number] => 06343042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'DRAM core refresh with reduced spike current' [patent_app_type] => B1 [patent_app_number] => 09/561592 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4493 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343042.pdf [firstpage_image] =>[orig_patent_app_number] => 09561592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561592
DRAM core refresh with reduced spike current Apr 26, 2000 Issued
Array ( [id] => 4262755 [patent_doc_number] => 06222768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Auto adjusting window placement scheme for an NROM virtual ground array' [patent_app_type] => 1 [patent_app_number] => 9/557832 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6329 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222768.pdf [firstpage_image] =>[orig_patent_app_number] => 557832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557832
Auto adjusting window placement scheme for an NROM virtual ground array Apr 25, 2000 Issued
Array ( [id] => 1589954 [patent_doc_number] => 06359806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Memory device' [patent_app_type] => B1 [patent_app_number] => 09/558036 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6921 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359806.pdf [firstpage_image] =>[orig_patent_app_number] => 09558036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558036
Memory device Apr 25, 2000 Issued
Array ( [id] => 4419191 [patent_doc_number] => 06301161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Programming flash memory analog storage using coarse-and-fine sequence' [patent_app_type] => 1 [patent_app_number] => 9/558432 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301161.pdf [firstpage_image] =>[orig_patent_app_number] => 558432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558432
Programming flash memory analog storage using coarse-and-fine sequence Apr 24, 2000 Issued
Array ( [id] => 4344867 [patent_doc_number] => 06314034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Application specific event based semiconductor memory test system' [patent_app_type] => 1 [patent_app_number] => 9/549734 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8384 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314034.pdf [firstpage_image] =>[orig_patent_app_number] => 549734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/549734
Application specific event based semiconductor memory test system Apr 13, 2000 Issued
Array ( [id] => 4262942 [patent_doc_number] => 06222781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Semiconductor integrated circuit device capable of externally applying power supply potential to internal circuit while restricting noise' [patent_app_type] => 1 [patent_app_number] => 9/549934 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6720 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222781.pdf [firstpage_image] =>[orig_patent_app_number] => 549934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/549934
Semiconductor integrated circuit device capable of externally applying power supply potential to internal circuit while restricting noise Apr 13, 2000 Issued
Array ( [id] => 4369220 [patent_doc_number] => 06219269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor memory device capable of improving read operation speed' [patent_app_type] => 1 [patent_app_number] => 9/547934 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 4106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219269.pdf [firstpage_image] =>[orig_patent_app_number] => 547934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547934
Semiconductor memory device capable of improving read operation speed Apr 10, 2000 Issued
Array ( [id] => 4305331 [patent_doc_number] => 06236614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Semiconductor memory with local phase generation from global phase signals and local isolation signals' [patent_app_type] => 1 [patent_app_number] => 9/544759 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1593 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236614.pdf [firstpage_image] =>[orig_patent_app_number] => 544759 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/544759
Semiconductor memory with local phase generation from global phase signals and local isolation signals Apr 4, 2000 Issued
Array ( [id] => 4358577 [patent_doc_number] => 06285575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Shadow RAM cell and non-volatile memory device employing ferroelectric capacitor and control method therefor' [patent_app_type] => 1 [patent_app_number] => 9/542230 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7492 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285575.pdf [firstpage_image] =>[orig_patent_app_number] => 542230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542230
Shadow RAM cell and non-volatile memory device employing ferroelectric capacitor and control method therefor Apr 3, 2000 Issued
Array ( [id] => 4290927 [patent_doc_number] => 06282120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Non-volatile memory with improved sensing and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/536930 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 8554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282120.pdf [firstpage_image] =>[orig_patent_app_number] => 536930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536930
Non-volatile memory with improved sensing and method therefor Mar 26, 2000 Issued
Array ( [id] => 4369511 [patent_doc_number] => 06219289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Data writing apparatus, data writing method, and tester' [patent_app_type] => 1 [patent_app_number] => 9/533734 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6561 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219289.pdf [firstpage_image] =>[orig_patent_app_number] => 533734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533734
Data writing apparatus, data writing method, and tester Mar 22, 2000 Issued
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