Search

Dirk Wright

Examiner (ID: 11999, Phone: (571)272-7098 , Office: P/3659 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3656, 3659, 3622, 3655, 2899, 3681
Total Applications
4396
Issued Applications
4127
Pending Applications
57
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4311382 [patent_doc_number] => 06188237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Impedance matching circuit, high speed semiconductor integrated circuit employing the same and computer system employing the integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/316162 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10618 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188237.pdf [firstpage_image] =>[orig_patent_app_number] => 316162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316162
Impedance matching circuit, high speed semiconductor integrated circuit employing the same and computer system employing the integrated circuit May 20, 1999 Issued
Array ( [id] => 4267177 [patent_doc_number] => 06204694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals' [patent_app_type] => 1 [patent_app_number] => 9/316197 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 10325 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204694.pdf [firstpage_image] =>[orig_patent_app_number] => 316197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316197
Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals May 20, 1999 Issued
Array ( [id] => 4165221 [patent_doc_number] => 06114876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Translator switch transistor with output voltage adjusted to match a reference by controlling gate and substrate charge pumps' [patent_app_type] => 1 [patent_app_number] => 9/315775 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114876.pdf [firstpage_image] =>[orig_patent_app_number] => 315775 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315775
Translator switch transistor with output voltage adjusted to match a reference by controlling gate and substrate charge pumps May 19, 1999 Issued
Array ( [id] => 4247437 [patent_doc_number] => 06118714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor memory circuit with bit lines discharging means' [patent_app_type] => 1 [patent_app_number] => 9/314080 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5247 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118714.pdf [firstpage_image] =>[orig_patent_app_number] => 314080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314080
Semiconductor memory circuit with bit lines discharging means May 18, 1999 Issued
Array ( [id] => 4204588 [patent_doc_number] => 06044013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/314446 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 98 [patent_figures_cnt] => 124 [patent_no_of_words] => 64017 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044013.pdf [firstpage_image] =>[orig_patent_app_number] => 314446 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314446
Nonvolatile semiconductor memory device May 18, 1999 Issued
Array ( [id] => 4169986 [patent_doc_number] => 06104632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Magnetic thin film memory and recording and reproducing method and apparatus using such a memory' [patent_app_type] => 1 [patent_app_number] => 9/313176 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 14271 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104632.pdf [firstpage_image] =>[orig_patent_app_number] => 313176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313176
Magnetic thin film memory and recording and reproducing method and apparatus using such a memory May 17, 1999 Issued
Array ( [id] => 4364284 [patent_doc_number] => 06175248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Pulse width distortion correction logic level converter' [patent_app_type] => 1 [patent_app_number] => 9/314426 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3131 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175248.pdf [firstpage_image] =>[orig_patent_app_number] => 314426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314426
Pulse width distortion correction logic level converter May 17, 1999 Issued
Array ( [id] => 4267007 [patent_doc_number] => 06204683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Apparatus and method for reducing crosstalk in an integrated circuit which includes a signal bus' [patent_app_type] => 1 [patent_app_number] => 9/313742 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3401 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204683.pdf [firstpage_image] =>[orig_patent_app_number] => 313742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313742
Apparatus and method for reducing crosstalk in an integrated circuit which includes a signal bus May 17, 1999 Issued
Array ( [id] => 4261822 [patent_doc_number] => 06137732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor memory device having voltage boosting circuit' [patent_app_type] => 1 [patent_app_number] => 9/313078 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6882 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137732.pdf [firstpage_image] =>[orig_patent_app_number] => 313078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313078
Semiconductor memory device having voltage boosting circuit May 16, 1999 Issued
Array ( [id] => 4365553 [patent_doc_number] => 06169445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Current mode transmitter' [patent_app_type] => 1 [patent_app_number] => 9/312905 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3525 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169445.pdf [firstpage_image] =>[orig_patent_app_number] => 312905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312905
Current mode transmitter May 16, 1999 Issued
Array ( [id] => 4192507 [patent_doc_number] => 06094063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method for level shifting logic signal voltage levels' [patent_app_type] => 1 [patent_app_number] => 9/312023 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8263 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094063.pdf [firstpage_image] =>[orig_patent_app_number] => 312023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312023
Method for level shifting logic signal voltage levels May 13, 1999 Issued
Array ( [id] => 4311469 [patent_doc_number] => 06188241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface' [patent_app_type] => 1 [patent_app_number] => 9/311448 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3599 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188241.pdf [firstpage_image] =>[orig_patent_app_number] => 311448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311448
Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface May 13, 1999 Issued
Array ( [id] => 4202236 [patent_doc_number] => 06130850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Semiconductor storage device with serial-parallel conversion function' [patent_app_type] => 1 [patent_app_number] => 9/311978 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2943 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130850.pdf [firstpage_image] =>[orig_patent_app_number] => 311978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311978
Semiconductor storage device with serial-parallel conversion function May 13, 1999 Issued
Array ( [id] => 4299684 [patent_doc_number] => 06236238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Output buffer with independently controllable current mirror legs' [patent_app_type] => 1 [patent_app_number] => 9/311242 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5886 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236238.pdf [firstpage_image] =>[orig_patent_app_number] => 311242 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311242
Output buffer with independently controllable current mirror legs May 12, 1999 Issued
Array ( [id] => 4302479 [patent_doc_number] => 06181164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Linear feedback shift register in a programmable gate array' [patent_app_type] => 1 [patent_app_number] => 9/312369 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181164.pdf [firstpage_image] =>[orig_patent_app_number] => 312369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312369
Linear feedback shift register in a programmable gate array May 12, 1999 Issued
Array ( [id] => 4217045 [patent_doc_number] => 06078540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Selective power distribution circuit for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/304299 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6763 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078540.pdf [firstpage_image] =>[orig_patent_app_number] => 304299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304299
Selective power distribution circuit for an integrated circuit May 2, 1999 Issued
Array ( [id] => 4102884 [patent_doc_number] => 06134164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Sensing circuit for a memory cell array' [patent_app_type] => 1 [patent_app_number] => 9/296876 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134164.pdf [firstpage_image] =>[orig_patent_app_number] => 296876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296876
Sensing circuit for a memory cell array Apr 21, 1999 Issued
Array ( [id] => 4165970 [patent_doc_number] => 06125077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Apparatus and method for providing a quiet time before analog signal sampling in a mixed signal integrated circuit employing synchronous and asynchronous clocking' [patent_app_type] => 1 [patent_app_number] => 9/294576 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5384 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125077.pdf [firstpage_image] =>[orig_patent_app_number] => 294576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294576
Apparatus and method for providing a quiet time before analog signal sampling in a mixed signal integrated circuit employing synchronous and asynchronous clocking Apr 19, 1999 Issued
Array ( [id] => 4159820 [patent_doc_number] => 06064624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Circuit and method for eliminating idle cycles in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/290727 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 6518 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064624.pdf [firstpage_image] =>[orig_patent_app_number] => 290727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290727
Circuit and method for eliminating idle cycles in a memory device Apr 11, 1999 Issued
Array ( [id] => 4185097 [patent_doc_number] => 06141241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Universal memory element with systems employing same and apparatus and method for reading, writing and programming same' [patent_app_type] => 1 [patent_app_number] => 9/289713 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 13536 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141241.pdf [firstpage_image] =>[orig_patent_app_number] => 289713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289713
Universal memory element with systems employing same and apparatus and method for reading, writing and programming same Apr 11, 1999 Issued
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