Dirk Wright

Array ( [id] => 4165802 [patent_doc_number] => 06125066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Circuit configuration and method for automatic recognition and elimination of word line/bit line short circuits' [patent_app_type] => 1 [patent_app_number] => 9/277280 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2402 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125066.pdf [firstpage_image] =>[orig_patent_app_number] => 277280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102578 [patent_doc_number] => 06134142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Redundancy method and a device for a non-volatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/276776 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8583 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134142.pdf [firstpage_image] =>[orig_patent_app_number] => 276776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110742 [patent_doc_number] => 06067257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Semiconductor integrated circuit device having step-down voltage circuit' [patent_app_type] => 1 [patent_app_number] => 9/270677 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 14399 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067257.pdf [firstpage_image] =>[orig_patent_app_number] => 270677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170436 [patent_doc_number] => 06157583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Integrated circuit memory having a fuse detect circuit and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/261876 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157583.pdf [firstpage_image] =>[orig_patent_app_number] => 261876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373833 [patent_doc_number] => 06256225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Construction and application for non-volatile reprogrammable switches' [patent_app_type] => 1 [patent_app_number] => 9/261479 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6518 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256225.pdf [firstpage_image] =>[orig_patent_app_number] => 261479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202138 [patent_doc_number] => 06130844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Low consumption boosted voltage driving circuit' [patent_app_type] => 1 [patent_app_number] => 9/257682 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2717 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130844.pdf [firstpage_image] =>[orig_patent_app_number] => 257682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120802 [patent_doc_number] => 06058068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Write driver with locally generated reset pulse' [patent_app_type] => 1 [patent_app_number] => 9/258080 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4182 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058068.pdf [firstpage_image] =>[orig_patent_app_number] => 258080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102648 [patent_doc_number] => 06134147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/252680 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3616 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134147.pdf [firstpage_image] =>[orig_patent_app_number] => 252680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153166 [patent_doc_number] => 06061290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method and apparatus for simultaneous memory subarray testing' [patent_app_type] => 1 [patent_app_number] => 9/250593 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1998 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061290.pdf [firstpage_image] =>[orig_patent_app_number] => 250593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4093330 [patent_doc_number] => 06055180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Electrically addressable passive device, method for electrical addressing of the same and uses of the device and the method' [patent_app_type] => 1 [patent_app_number] => 9/147680 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8801 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055180.pdf [firstpage_image] =>[orig_patent_app_number] => 147680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202100 [patent_doc_number] => 06154387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor memory device utilizing a polarization state of a ferroelectric film' [patent_app_type] => 1 [patent_app_number] => 9/249477 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5618 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154387.pdf [firstpage_image] =>[orig_patent_app_number] => 249477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4169895 [patent_doc_number] => 06108240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions' [patent_app_type] => 1 [patent_app_number] => 9/243977 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5815 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108240.pdf [firstpage_image] =>[orig_patent_app_number] => 243977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102776 [patent_doc_number] => 06134156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method for initiating a retrieval procedure in virtual ground arrays' [patent_app_type] => 1 [patent_app_number] => 9/246776 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4820 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134156.pdf [firstpage_image] =>[orig_patent_app_number] => 246776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250552 [patent_doc_number] => 06081456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Bit line control circuit for a memory array using 2-bit non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 9/243976 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 12228 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081456.pdf [firstpage_image] =>[orig_patent_app_number] => 243976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4231621 [patent_doc_number] => 06088284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Memory chip having multiple input/output system' [patent_app_type] => 1 [patent_app_number] => 9/239780 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5220 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088284.pdf [firstpage_image] =>[orig_patent_app_number] => 239780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170116 [patent_doc_number] => 06104641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Switchable multi bit semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/228980 [patent_app_country] => US [patent_app_date] => 1999-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 8343 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104641.pdf [firstpage_image] =>[orig_patent_app_number] => 228980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144647 [patent_doc_number] => 06034915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Memory with variable write driver operation' [patent_app_type] => 1 [patent_app_number] => 9/228581 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3111 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034915.pdf [firstpage_image] =>[orig_patent_app_number] => 228581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187974 [patent_doc_number] => 06084820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Dual port memory device with vertical shielding' [patent_app_type] => 1 [patent_app_number] => 9/226777 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084820.pdf [firstpage_image] =>[orig_patent_app_number] => 226777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4192019 [patent_doc_number] => 06038179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Multiple repair size redundancy' [patent_app_type] => 1 [patent_app_number] => 9/224776 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2083 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038179.pdf [firstpage_image] =>[orig_patent_app_number] => 224776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204887 [patent_doc_number] => 06044033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'NOR-type nonvolatile semiconductor memory device and a method for reading therefrom' [patent_app_type] => 1 [patent_app_number] => 9/221978 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3520 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044033.pdf [firstpage_image] =>[orig_patent_app_number] => 221978 [rel_patent_id] =>[rel_patent_doc_number] =>)