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Diva Kakar Chander

Examiner (ID: 18550)

Most Active Art Unit
3763
Art Unit(s)
3763
Total Applications
355
Issued Applications
281
Pending Applications
2
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19071973 [patent_doc_number] => 20240106399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => LOGIC OPERATION CIRCUIT, DIFFERENTIAL AMPLIFIER CIRCUIT, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/527506 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527506
Logic operation circuit, differential amplifier circuit, and electronic device Dec 3, 2023 Issued
Array ( [id] => 19071973 [patent_doc_number] => 20240106399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => LOGIC OPERATION CIRCUIT, DIFFERENTIAL AMPLIFIER CIRCUIT, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/527506 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527506
Logic operation circuit, differential amplifier circuit, and electronic device Dec 3, 2023 Issued
Array ( [id] => 19237843 [patent_doc_number] => 20240195038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => HYBRID PLANAR COMBINER FOR PLANAR SOLID STATE POWER AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 18/525923 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525923
HYBRID PLANAR COMBINER FOR PLANAR SOLID STATE POWER AMPLIFIERS Nov 30, 2023 Pending
Array ( [id] => 19238210 [patent_doc_number] => 20240195405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => RECEIVER CIRCUIT, CORRESPONDING ISOLATED DRIVER DEVICE, ELECTRONIC SYSTEM AND METHOD OF DECODING A DIFFERENTIAL SIGNAL INTO A DIGITAL OUTPUT SIGNAL [patent_app_type] => utility [patent_app_number] => 18/526776 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526776
Receiver circuit, corresponding isolated driver device, electronic system and method of decoding a differential signal into a digital output signal Nov 30, 2023 Issued
Array ( [id] => 20045671 [patent_doc_number] => 20250183893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => BUFFER CIRCUIT WITH THRESHOLD VOLTAGE CANCELLATION [patent_app_type] => utility [patent_app_number] => 18/525655 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525655
BUFFER CIRCUIT WITH THRESHOLD VOLTAGE CANCELLATION Nov 29, 2023 Pending
Array ( [id] => 20375800 [patent_doc_number] => 12483246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Self timed level shifter circuit [patent_app_type] => utility [patent_app_number] => 18/515609 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515609 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515609
Self timed level shifter circuit Nov 20, 2023 Issued
Array ( [id] => 20346486 [patent_doc_number] => 12470222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Digital duty cycle calibration [patent_app_type] => utility [patent_app_number] => 18/516084 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516084 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516084
Digital duty cycle calibration Nov 20, 2023 Issued
Array ( [id] => 20333360 [patent_doc_number] => 12463647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Level shifter and multi-voltage-domain circuits [patent_app_type] => utility [patent_app_number] => 18/515621 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515621 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515621
Level shifter and multi-voltage-domain circuits Nov 20, 2023 Issued
Array ( [id] => 20333360 [patent_doc_number] => 12463647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Level shifter and multi-voltage-domain circuits [patent_app_type] => utility [patent_app_number] => 18/515621 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515621 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515621
Level shifter and multi-voltage-domain circuits Nov 20, 2023 Issued
Array ( [id] => 20029558 [patent_doc_number] => 20250167780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SWITCHING CIRCUIT WITH A TRANSISTOR HAVING MULTIPLE PULL DOWN PATHS [patent_app_type] => utility [patent_app_number] => 18/512493 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512493
SWITCHING CIRCUIT WITH A TRANSISTOR HAVING MULTIPLE PULL DOWN PATHS Nov 16, 2023 Pending
Array ( [id] => 20029558 [patent_doc_number] => 20250167780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SWITCHING CIRCUIT WITH A TRANSISTOR HAVING MULTIPLE PULL DOWN PATHS [patent_app_type] => utility [patent_app_number] => 18/512493 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512493
SWITCHING CIRCUIT WITH A TRANSISTOR HAVING MULTIPLE PULL DOWN PATHS Nov 16, 2023 Pending
Array ( [id] => 19206936 [patent_doc_number] => 20240178835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => ISOLATED DRIVER DEVICE, CORRESPONDING ELECTRONIC SYSTEM AND METHOD OF TRANSMITTING A DATA SIGNAL ACROSS A GALVANIC ISOLATION BARRIER [patent_app_type] => utility [patent_app_number] => 18/508011 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508011
ISOLATED DRIVER DEVICE, CORRESPONDING ELECTRONIC SYSTEM AND METHOD OF TRANSMITTING A DATA SIGNAL ACROSS A GALVANIC ISOLATION BARRIER Nov 12, 2023 Pending
Array ( [id] => 19206936 [patent_doc_number] => 20240178835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => ISOLATED DRIVER DEVICE, CORRESPONDING ELECTRONIC SYSTEM AND METHOD OF TRANSMITTING A DATA SIGNAL ACROSS A GALVANIC ISOLATION BARRIER [patent_app_type] => utility [patent_app_number] => 18/508011 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508011
ISOLATED DRIVER DEVICE, CORRESPONDING ELECTRONIC SYSTEM AND METHOD OF TRANSMITTING A DATA SIGNAL ACROSS A GALVANIC ISOLATION BARRIER Nov 12, 2023 Pending
Array ( [id] => 20020636 [patent_doc_number] => 20250158858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => HYBRID CLOCKING SCHEME FOR SERDES PHYSICAL LAYER CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/505477 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505477
Hybrid clocking scheme for SERDES physical layer circuits Nov 8, 2023 Issued
Array ( [id] => 19560667 [patent_doc_number] => 20240372459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DRIVING DEVICE [patent_app_type] => utility [patent_app_number] => 18/505318 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505318
Driving circuit device Nov 8, 2023 Issued
Array ( [id] => 19560667 [patent_doc_number] => 20240372459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DRIVING DEVICE [patent_app_type] => utility [patent_app_number] => 18/505318 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505318
Driving circuit device Nov 8, 2023 Issued
Array ( [id] => 20202844 [patent_doc_number] => 12405622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Voltage detector in data communication interface [patent_app_type] => utility [patent_app_number] => 18/498927 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2531 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498927 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498927
Voltage detector in data communication interface Oct 30, 2023 Issued
Array ( [id] => 19900682 [patent_doc_number] => 12278627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Synchronization of sensor output samples [patent_app_type] => utility [patent_app_number] => 18/384220 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384220
Synchronization of sensor output samples Oct 25, 2023 Issued
Array ( [id] => 20003227 [patent_doc_number] => 20250141449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => OFF-CHIP DRIVER AND DRIVING CIRCUIT FOR PROVIDING MATCHING RESISTANCE VALUE [patent_app_type] => utility [patent_app_number] => 18/493817 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493817
Off-chip driver and driving circuit for providing matching resistance value Oct 24, 2023 Issued
Array ( [id] => 20003227 [patent_doc_number] => 20250141449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => OFF-CHIP DRIVER AND DRIVING CIRCUIT FOR PROVIDING MATCHING RESISTANCE VALUE [patent_app_type] => utility [patent_app_number] => 18/493817 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493817
Off-chip driver and driving circuit for providing matching resistance value Oct 24, 2023 Issued
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