Search

Do H. Yoo

Examiner (ID: 19244)

Most Active Art Unit
2511
Art Unit(s)
2818, 2502, 2824, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
59/971194 Test ads for efsweb1.3 Dec 31, 2017 Pending
59/973266 Test ads for efsweb1.3 Dec 31, 2017 Pending
59/966946 test ads for Adobe Reader 9.1.1 Dec 31, 2017 Pending
59/973267 Test ads for efsweb1.3 Dec 31, 2017 Pending
Array ( [id] => 8433646 [patent_doc_number] => RE043729 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2012-10-09 [patent_title] => 'Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing' [patent_app_type] => reissue [patent_app_number] => 13/092453 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 14456 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092453
Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing Apr 21, 2011 Issued
Array ( [id] => 8354999 [patent_doc_number] => 08250340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Processor for executing highly efficient VLIW' [patent_app_type] => utility [patent_app_number] => 12/705300 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 10142 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12705300 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/705300
Processor for executing highly efficient VLIW Feb 11, 2010 Issued
Array ( [id] => 7547903 [patent_doc_number] => 08055884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Method and apparatus for augmenting a pipeline with a bubble-removal circuit' [patent_app_type] => utility [patent_app_number] => 12/629540 [patent_app_country] => US [patent_app_date] => 2009-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6033 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055884.pdf [firstpage_image] =>[orig_patent_app_number] => 12629540 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/629540
Method and apparatus for augmenting a pipeline with a bubble-removal circuit Dec 1, 2009 Issued
Array ( [id] => 5459723 [patent_doc_number] => 20090259875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'Store Clock and Store Clock Fast Instruction Execution' [patent_app_type] => utility [patent_app_number] => 12/488670 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8894 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20090259875.pdf [firstpage_image] =>[orig_patent_app_number] => 12488670 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488670
Store Clock and Store Clock Fast Instruction Execution Jun 21, 2009 Abandoned
Array ( [id] => 4641937 [patent_doc_number] => 08019971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Processor for executing highly efficient VLIW' [patent_app_type] => utility [patent_app_number] => 12/418965 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 10115 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019971.pdf [firstpage_image] =>[orig_patent_app_number] => 12418965 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/418965
Processor for executing highly efficient VLIW Apr 5, 2009 Issued
Array ( [id] => 5548137 [patent_doc_number] => 20090158014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor' [patent_app_type] => utility [patent_app_number] => 12/393257 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6930 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158014.pdf [firstpage_image] =>[orig_patent_app_number] => 12393257 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/393257
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Feb 25, 2009 Issued
Array ( [id] => 4616527 [patent_doc_number] => 07991980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Concurrent execution of instructions in a processing system' [patent_app_type] => utility [patent_app_number] => 12/254684 [patent_app_country] => US [patent_app_date] => 2008-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 13259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/991/07991980.pdf [firstpage_image] =>[orig_patent_app_number] => 12254684 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/254684
Concurrent execution of instructions in a processing system Oct 19, 2008 Issued
Array ( [id] => 5362914 [patent_doc_number] => 20090037708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'TARGET BRANCH PREDICTION USING CORRELATION OF LOCAL TARGET HISTORIES' [patent_app_type] => utility [patent_app_number] => 12/246282 [patent_app_country] => US [patent_app_date] => 2008-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3531 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037708.pdf [firstpage_image] =>[orig_patent_app_number] => 12246282 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/246282
Target branch prediction using a plurality of tables Oct 5, 2008 Issued
Array ( [id] => 4527595 [patent_doc_number] => 07934078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor' [patent_app_type] => utility [patent_app_number] => 12/212361 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6927 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934078.pdf [firstpage_image] =>[orig_patent_app_number] => 12212361 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/212361
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Sep 16, 2008 Issued
Array ( [id] => 5351459 [patent_doc_number] => 20090006820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => ' Issue Unit for Placing a Processor into a Gradual Slow Mode of Operation' [patent_app_type] => utility [patent_app_number] => 12/207545 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9754 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006820.pdf [firstpage_image] =>[orig_patent_app_number] => 12207545 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/207545
Issue unit for placing a processor into a gradual slow mode of operation Sep 9, 2008 Issued
Array ( [id] => 5351456 [patent_doc_number] => 20090006817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Mechanisms for Placing a Processor into a Gradual Slow Mode of Operation' [patent_app_type] => utility [patent_app_number] => 12/204865 [patent_app_country] => US [patent_app_date] => 2008-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9033 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006817.pdf [firstpage_image] =>[orig_patent_app_number] => 12204865 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/204865
Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition Sep 4, 2008 Issued
Array ( [id] => 4825953 [patent_doc_number] => 20080229077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER' [patent_app_type] => utility [patent_app_number] => 12/127845 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4895 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229077.pdf [firstpage_image] =>[orig_patent_app_number] => 12127845 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127845
COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER May 27, 2008 Abandoned
Array ( [id] => 5339169 [patent_doc_number] => 20090055633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER' [patent_app_type] => utility [patent_app_number] => 12/127844 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4895 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055633.pdf [firstpage_image] =>[orig_patent_app_number] => 12127844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127844
COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER May 27, 2008 Abandoned
Array ( [id] => 343157 [patent_doc_number] => 07502918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-10 [patent_title] => 'Method and system for data dependent performance increment and power reduction' [patent_app_type] => utility [patent_app_number] => 12/058256 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2190 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502918.pdf [firstpage_image] =>[orig_patent_app_number] => 12058256 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/058256
Method and system for data dependent performance increment and power reduction Mar 27, 2008 Issued
Array ( [id] => 4462360 [patent_doc_number] => 07895419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Rotate then operate on selected bits facility and instructions therefore' [patent_app_type] => utility [patent_app_number] => 11/972679 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16087 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895419.pdf [firstpage_image] =>[orig_patent_app_number] => 11972679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972679
Rotate then operate on selected bits facility and instructions therefore Jan 10, 2008 Issued
Array ( [id] => 5344333 [patent_doc_number] => 20090182983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'Compare and Branch Facility and Instruction Therefore' [patent_app_type] => utility [patent_app_number] => 11/972666 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16401 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20090182983.pdf [firstpage_image] =>[orig_patent_app_number] => 11972666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972666
Compare and Branch Facility and Instruction Therefore Jan 10, 2008 Abandoned
Menu