Search

Do H. Yoo

Examiner (ID: 19244)

Most Active Art Unit
2511
Art Unit(s)
2818, 2502, 2824, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4310491 [patent_doc_number] => 06212627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'System for converting packed integer data into packed floating point data in reduced time' [patent_app_type] => 1 [patent_app_number] => 9/170365 [patent_app_country] => US [patent_app_date] => 1998-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4177 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212627.pdf [firstpage_image] =>[orig_patent_app_number] => 170365 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170365
System for converting packed integer data into packed floating point data in reduced time Oct 11, 1998 Issued
Array ( [id] => 1376022 [patent_doc_number] => 06578059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Methods and apparatus for controlling exponent range in floating-point calculations' [patent_app_type] => B1 [patent_app_number] => 09/169669 [patent_app_country] => US [patent_app_date] => 1998-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8549 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578059.pdf [firstpage_image] =>[orig_patent_app_number] => 09169669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169669
Methods and apparatus for controlling exponent range in floating-point calculations Oct 9, 1998 Issued
Array ( [id] => 4192705 [patent_doc_number] => 06141742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method for reducing number of bits used in storage of instruction address pointer values' [patent_app_type] => 1 [patent_app_number] => 9/166322 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 25733 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141742.pdf [firstpage_image] =>[orig_patent_app_number] => 166322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166322
Method for reducing number of bits used in storage of instruction address pointer values Oct 5, 1998 Issued
Array ( [id] => 4402412 [patent_doc_number] => 06279096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Digital signal processing memory logic unit using PLA to modify address and data bus output values' [patent_app_type] => 1 [patent_app_number] => 9/164965 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3769 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279096.pdf [firstpage_image] =>[orig_patent_app_number] => 164965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164965
Digital signal processing memory logic unit using PLA to modify address and data bus output values Sep 30, 1998 Issued
Array ( [id] => 4192772 [patent_doc_number] => 06141747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word' [patent_app_type] => 1 [patent_app_number] => 9/158465 [patent_app_country] => US [patent_app_date] => 1998-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12716 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141747.pdf [firstpage_image] =>[orig_patent_app_number] => 158465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158465
System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word Sep 21, 1998 Issued
Array ( [id] => 4424877 [patent_doc_number] => 06230263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Data processing system processor delay instruction' [patent_app_type] => 1 [patent_app_number] => 9/156376 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 10242 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230263.pdf [firstpage_image] =>[orig_patent_app_number] => 156376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156376
Data processing system processor delay instruction Sep 16, 1998 Issued
Array ( [id] => 4388521 [patent_doc_number] => 06275924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time' [patent_app_type] => 1 [patent_app_number] => 9/153370 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275924.pdf [firstpage_image] =>[orig_patent_app_number] => 153370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153370
System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time Sep 14, 1998 Issued
Array ( [id] => 1557361 [patent_doc_number] => 06349383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution' [patent_app_type] => B1 [patent_app_number] => 09/151006 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12650 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349383.pdf [firstpage_image] =>[orig_patent_app_number] => 09151006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/151006
System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution Sep 9, 1998 Issued
Array ( [id] => 4317967 [patent_doc_number] => 06185675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks' [patent_app_type] => 1 [patent_app_number] => 9/137579 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 18922 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185675.pdf [firstpage_image] =>[orig_patent_app_number] => 137579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137579
Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks Aug 20, 1998 Issued
Array ( [id] => 4281126 [patent_doc_number] => 06260136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Substitute register for use in a high speed data processor' [patent_app_type] => 1 [patent_app_number] => 9/135487 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4720 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260136.pdf [firstpage_image] =>[orig_patent_app_number] => 135487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135487
Substitute register for use in a high speed data processor Aug 17, 1998 Issued
Array ( [id] => 4304795 [patent_doc_number] => 06269431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Virtual storage and block level direct access of secondary storage for recovery of backup data' [patent_app_type] => 1 [patent_app_number] => 9/133564 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 15756 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269431.pdf [firstpage_image] =>[orig_patent_app_number] => 133564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/133564
Virtual storage and block level direct access of secondary storage for recovery of backup data Aug 12, 1998 Issued
09/121493 METHOD FOR RAPID COMMUNICATION WITHIN A PARALLEL COMPUTER SYSTEM, AND A PARALLEL COMPUTER SYSTEM OPERATED BY THE METHOD Jul 22, 1998 Abandoned
Array ( [id] => 4121482 [patent_doc_number] => 06023755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Computer with programmable arrays which are reconfigurable in response to instructions to be executed' [patent_app_type] => 1 [patent_app_number] => 9/120958 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 11143 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023755.pdf [firstpage_image] =>[orig_patent_app_number] => 120958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120958
Computer with programmable arrays which are reconfigurable in response to instructions to be executed Jul 21, 1998 Issued
Array ( [id] => 4192520 [patent_doc_number] => 06141732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Burst-loading of instructions into processor cache by execution of linked jump instructions embedded in cache line size blocks' [patent_app_type] => 1 [patent_app_number] => 9/118718 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17816 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141732.pdf [firstpage_image] =>[orig_patent_app_number] => 118718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118718
Burst-loading of instructions into processor cache by execution of linked jump instructions embedded in cache line size blocks Jul 16, 1998 Issued
Array ( [id] => 4252625 [patent_doc_number] => 06076155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets' [patent_app_type] => 1 [patent_app_number] => 9/100273 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8061 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076155.pdf [firstpage_image] =>[orig_patent_app_number] => 100273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100273
Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets Jun 18, 1998 Issued
Array ( [id] => 4304921 [patent_doc_number] => 06269439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Signal processor having pipeline processing that supresses the deterioration of processing efficiency and method of the same' [patent_app_type] => 1 [patent_app_number] => 9/096574 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5654 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269439.pdf [firstpage_image] =>[orig_patent_app_number] => 096574 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096574
Signal processor having pipeline processing that supresses the deterioration of processing efficiency and method of the same Jun 11, 1998 Issued
Array ( [id] => 4323541 [patent_doc_number] => 06189053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Communication control system utilizing a shared buffer managed by high and low level protocols' [patent_app_type] => 1 [patent_app_number] => 9/093396 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 7658 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189053.pdf [firstpage_image] =>[orig_patent_app_number] => 093396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093396
Communication control system utilizing a shared buffer managed by high and low level protocols Jun 8, 1998 Issued
Array ( [id] => 4292529 [patent_doc_number] => 06247118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry' [patent_app_type] => 1 [patent_app_number] => 9/092237 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6264 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247118.pdf [firstpage_image] =>[orig_patent_app_number] => 092237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092237
Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry Jun 4, 1998 Issued
Array ( [id] => 3970921 [patent_doc_number] => 06000000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Extendible method and apparatus for synchronizing multiple files on two different computer systems' [patent_app_type] => 1 [patent_app_number] => 9/072274 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6323 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000000.pdf [firstpage_image] =>[orig_patent_app_number] => 072274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072274
Extendible method and apparatus for synchronizing multiple files on two different computer systems May 3, 1998 Issued
Array ( [id] => 4171734 [patent_doc_number] => 06125444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all' [patent_app_type] => 1 [patent_app_number] => 9/070201 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2460 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125444.pdf [firstpage_image] =>[orig_patent_app_number] => 070201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070201
Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all Apr 29, 1998 Issued
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