Do H. Yoo

Array ( [id] => 3516518 [patent_doc_number] => 05570318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Semiconductor memory device incorporating redundancy memory cells' [patent_app_type] => 1 [patent_app_number] => 8/563940 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5950 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570318.pdf [firstpage_image] =>[orig_patent_app_number] => 563940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3521033 [patent_doc_number] => 05563836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Fast access multi-bit random access memory' [patent_app_type] => 1 [patent_app_number] => 8/563991 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8456 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563836.pdf [firstpage_image] =>[orig_patent_app_number] => 563991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3591957 [patent_doc_number] => 05581504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Non-volatile electrically erasable memory with PMOS transistor NAND gate structure' [patent_app_type] => 1 [patent_app_number] => 8/557442 [patent_app_country] => US [patent_app_date] => 1995-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4131 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581504.pdf [firstpage_image] =>[orig_patent_app_number] => 557442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3659264 [patent_doc_number] => 05606525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Data register structure and semiconductor integrated circuit device using the same' [patent_app_type] => 1 [patent_app_number] => 8/552459 [patent_app_country] => US [patent_app_date] => 1995-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 5776 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606525.pdf [firstpage_image] =>[orig_patent_app_number] => 552459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3667904 [patent_doc_number] => 05627781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/555144 [patent_app_country] => US [patent_app_date] => 1995-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8130 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627781.pdf [firstpage_image] =>[orig_patent_app_number] => 555144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3826140 [patent_doc_number] => 05771194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Memory circuit, data control circuit of memory circuit and address assigning circuit of memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/550740 [patent_app_country] => US [patent_app_date] => 1995-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 62 [patent_no_of_words] => 32845 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771194.pdf [firstpage_image] =>[orig_patent_app_number] => 550740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3844332 [patent_doc_number] => 05761113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Soft error suppressing resistance load type SRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/550348 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 5164 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761113.pdf [firstpage_image] =>[orig_patent_app_number] => 550348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867830 [patent_doc_number] => 05706244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Semiconductor memory device having shared sense amplifier arrays individually controlled for cache storage' [patent_app_type] => 1 [patent_app_number] => 8/549943 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9626 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706244.pdf [firstpage_image] =>[orig_patent_app_number] => 549943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3712805 [patent_doc_number] => 05646904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed' [patent_app_type] => 1 [patent_app_number] => 8/544540 [patent_app_country] => US [patent_app_date] => 1995-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10012 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646904.pdf [firstpage_image] =>[orig_patent_app_number] => 544540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3558337 [patent_doc_number] => 05555529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Power saving architecture for a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/542514 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2184 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555529.pdf [firstpage_image] =>[orig_patent_app_number] => 542514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3698011 [patent_doc_number] => 05691942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Semiconductor memory having extended data out function' [patent_app_type] => 1 [patent_app_number] => 8/541546 [patent_app_country] => US [patent_app_date] => 1995-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8107 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691942.pdf [firstpage_image] =>[orig_patent_app_number] => 541546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3644742 [patent_doc_number] => 05610867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'DRAM signal margin test method' [patent_app_type] => 1 [patent_app_number] => 8/535446 [patent_app_country] => US [patent_app_date] => 1995-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6558 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610867.pdf [firstpage_image] =>[orig_patent_app_number] => 535446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3727742 [patent_doc_number] => 05617365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Semiconductor device having redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 8/535574 [patent_app_country] => US [patent_app_date] => 1995-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 36 [patent_no_of_words] => 16789 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617365.pdf [firstpage_image] =>[orig_patent_app_number] => 535574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3635126 [patent_doc_number] => 05608672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Correction method leading to a uniform threshold voltage distribution for a flash eprom' [patent_app_type] => 1 [patent_app_number] => 8/534141 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3703 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608672.pdf [firstpage_image] =>[orig_patent_app_number] => 534141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3520905 [patent_doc_number] => 05563827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Wordline driver for flash PLD' [patent_app_type] => 1 [patent_app_number] => 8/533412 [patent_app_country] => US [patent_app_date] => 1995-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8235 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563827.pdf [firstpage_image] =>[orig_patent_app_number] => 533412 [rel_patent_id] =>[rel_patent_doc_number] =>)