Search

Do H. Yoo

Examiner (ID: 19244)

Most Active Art Unit
2511
Art Unit(s)
2818, 2502, 2824, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4179424 [patent_doc_number] => 06115807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued' [patent_app_type] => 1 [patent_app_number] => 8/994516 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4389 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115807.pdf [firstpage_image] =>[orig_patent_app_number] => 994516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994516
Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued Dec 18, 1997 Issued
Array ( [id] => 4114703 [patent_doc_number] => 06049865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method and apparatus for implementing floating point projection instructions' [patent_app_type] => 1 [patent_app_number] => 8/993514 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5937 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049865.pdf [firstpage_image] =>[orig_patent_app_number] => 993514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993514
Method and apparatus for implementing floating point projection instructions Dec 17, 1997 Issued
Array ( [id] => 4211725 [patent_doc_number] => 06044458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'System for monitoring program flow utilizing fixwords stored sequentially to opcodes' [patent_app_type] => 1 [patent_app_number] => 8/989673 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4364 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044458.pdf [firstpage_image] =>[orig_patent_app_number] => 989673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989673
System for monitoring program flow utilizing fixwords stored sequentially to opcodes Dec 11, 1997 Issued
Array ( [id] => 4160648 [patent_doc_number] => 06061775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types' [patent_app_type] => 1 [patent_app_number] => 8/989793 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12599 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061775.pdf [firstpage_image] =>[orig_patent_app_number] => 989793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989793
Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types Dec 11, 1997 Issued
Array ( [id] => 4117790 [patent_doc_number] => 06098121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Data transfer apparatus with improved throughput due to reduced processing overhead in interrupt process' [patent_app_type] => 1 [patent_app_number] => 8/984429 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 7947 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098121.pdf [firstpage_image] =>[orig_patent_app_number] => 984429 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984429
Data transfer apparatus with improved throughput due to reduced processing overhead in interrupt process Dec 2, 1997 Issued
Array ( [id] => 4224268 [patent_doc_number] => 06079017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for loading sub-processor in system having a plurality of sub-processors with respect to main processor' [patent_app_type] => 1 [patent_app_number] => 8/982572 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4095 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079017.pdf [firstpage_image] =>[orig_patent_app_number] => 982572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982572
Method for loading sub-processor in system having a plurality of sub-processors with respect to main processor Dec 1, 1997 Issued
Array ( [id] => 3962057 [patent_doc_number] => 05974540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing' [patent_app_type] => 1 [patent_app_number] => 8/980676 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 14071 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974540.pdf [firstpage_image] =>[orig_patent_app_number] => 980676 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980676
Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing Nov 30, 1997 Issued
Array ( [id] => 4167741 [patent_doc_number] => 06065131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Multi-speed DSP kernel and clock mechanism' [patent_app_type] => 1 [patent_app_number] => 8/979530 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7220 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065131.pdf [firstpage_image] =>[orig_patent_app_number] => 979530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979530
Multi-speed DSP kernel and clock mechanism Nov 25, 1997 Issued
Array ( [id] => 3973745 [patent_doc_number] => 05978909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'System for speculative branch target prediction having a dynamic prediction history buffer and a static prediction history buffer' [patent_app_type] => 1 [patent_app_number] => 8/979579 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7624 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978909.pdf [firstpage_image] =>[orig_patent_app_number] => 979579 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979579
System for speculative branch target prediction having a dynamic prediction history buffer and a static prediction history buffer Nov 25, 1997 Issued
Array ( [id] => 4426943 [patent_doc_number] => 06195748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Apparatus for sampling instruction execution information in a processor pipeline' [patent_app_type] => 1 [patent_app_number] => 8/979033 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 15314 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195748.pdf [firstpage_image] =>[orig_patent_app_number] => 979033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979033
Apparatus for sampling instruction execution information in a processor pipeline Nov 25, 1997 Issued
Array ( [id] => 4215679 [patent_doc_number] => 06014737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Method and system for allowing a processor to perform read bypassing while automatically maintaining input/output data integrity' [patent_app_type] => 1 [patent_app_number] => 8/974072 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8669 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014737.pdf [firstpage_image] =>[orig_patent_app_number] => 974072 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974072
Method and system for allowing a processor to perform read bypassing while automatically maintaining input/output data integrity Nov 18, 1997 Issued
Array ( [id] => 4026186 [patent_doc_number] => 05941981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'System for using a data history table to select among multiple data prefetch algorithms' [patent_app_type] => 1 [patent_app_number] => 8/963276 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941981.pdf [firstpage_image] =>[orig_patent_app_number] => 963276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963276
System for using a data history table to select among multiple data prefetch algorithms Nov 2, 1997 Issued
Array ( [id] => 4057664 [patent_doc_number] => 05996067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead' [patent_app_type] => 1 [patent_app_number] => 8/959158 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 10 [patent_no_of_words] => 10622 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996067.pdf [firstpage_image] =>[orig_patent_app_number] => 959158 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959158
Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead Oct 27, 1997 Issued
Array ( [id] => 4085443 [patent_doc_number] => 06009512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Mechanism for forwarding operands based on predicated instructions' [patent_app_type] => 1 [patent_app_number] => 8/958477 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7351 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009512.pdf [firstpage_image] =>[orig_patent_app_number] => 958477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958477
Mechanism for forwarding operands based on predicated instructions Oct 26, 1997 Issued
Array ( [id] => 4109603 [patent_doc_number] => 06134608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Apparatus for providing multiple network services using a single serial communications port' [patent_app_type] => 1 [patent_app_number] => 8/955208 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3832 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134608.pdf [firstpage_image] =>[orig_patent_app_number] => 955208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955208
Apparatus for providing multiple network services using a single serial communications port Oct 20, 1997 Issued
Array ( [id] => 3928775 [patent_doc_number] => 06002853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'System for generating graphics in response to a database search' [patent_app_type] => 1 [patent_app_number] => 8/951064 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5402 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002853.pdf [firstpage_image] =>[orig_patent_app_number] => 951064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/951064
System for generating graphics in response to a database search Oct 14, 1997 Issued
Array ( [id] => 3987679 [patent_doc_number] => 05922065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Processor utilizing a template field for encoding instruction sequences in a wide-word format' [patent_app_type] => 1 [patent_app_number] => 8/949279 [patent_app_country] => US [patent_app_date] => 1997-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2670 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/922/05922065.pdf [firstpage_image] =>[orig_patent_app_number] => 949279 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949279
Processor utilizing a template field for encoding instruction sequences in a wide-word format Oct 12, 1997 Issued
Array ( [id] => 1587459 [patent_doc_number] => 06425068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (EPGAS)' [patent_app_type] => B1 [patent_app_number] => 08/946810 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 8202 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425068.pdf [firstpage_image] =>[orig_patent_app_number] => 08946810 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946810
UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (EPGAS) Oct 7, 1997 Issued
Array ( [id] => 4114770 [patent_doc_number] => 06049869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method and system for detecting and identifying a text or data encoding system' [patent_app_type] => 1 [patent_app_number] => 8/943919 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049869.pdf [firstpage_image] =>[orig_patent_app_number] => 943919 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/943919
Method and system for detecting and identifying a text or data encoding system Oct 2, 1997 Issued
Array ( [id] => 4121540 [patent_doc_number] => 06023759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'System for observing internal processor events utilizing a pipeline data path to pipeline internally generated signals representative of the event' [patent_app_type] => 1 [patent_app_number] => 8/940733 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4811 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023759.pdf [firstpage_image] =>[orig_patent_app_number] => 940733 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940733
System for observing internal processor events utilizing a pipeline data path to pipeline internally generated signals representative of the event Sep 29, 1997 Issued
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